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| author | Tristan Gingold <tgingold@free.fr> | 2020-02-18 20:26:50 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-02-18 20:27:12 +0100 |
| commit | 493fe4337300dbcfd796715bd7268347ba849950 (patch) | |
| tree | 9bb516d249d51eb4e1f1cfa6cb531898a4ccc82c /src/std_names.adb | |
| parent | 26aefc178f1f2d1eee9f0e48d919adb56b274466 (diff) | |
| download | ghdl-493fe4337300dbcfd796715bd7268347ba849950.tar.gz ghdl-493fe4337300dbcfd796715bd7268347ba849950.tar.bz2 ghdl-493fe4337300dbcfd796715bd7268347ba849950.zip | |
vhdl: recognize conversion functions from std_logic_1164
Diffstat (limited to 'src/std_names.adb')
| -rw-r--r-- | src/std_names.adb | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/std_names.adb b/src/std_names.adb index d8d71b29b..aaad7ab51 100644 --- a/src/std_names.adb +++ b/src/std_names.adb @@ -643,7 +643,11 @@ package body Std_Names is Def ("shift_right", Name_Shift_Right); Def ("rotate_left", Name_Rotate_Left); Def ("rotate_right", Name_Rotate_Right); + Def ("to_bit", Name_To_Bit); Def ("to_bitvector", Name_To_Bitvector); + Def ("to_stdulogic", Name_To_Stdulogic); + Def ("to_stdlogicvector", Name_To_Stdlogicvector); + Def ("to_stdulogicvector", Name_To_Stdulogicvector); Def ("is_x", Name_Is_X); Def ("conv_signed", Name_Conv_Signed); Def ("conv_unsigned", Name_Conv_Unsigned); |