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| author | Tristan Gingold <tgingold@free.fr> | 2022-09-07 04:56:58 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-09-07 04:56:58 +0200 |
| commit | d646114db387b69e2fe92a1c68c2c27c35f7dc5f (patch) | |
| tree | effc33716fc1fba6af4f7fc05689a67bc1a58a61 /src/simul/simul-vhdl_simul.adb | |
| parent | 68a7010349341dfaa8aa7b8b27701bf639ea0857 (diff) | |
| download | ghdl-d646114db387b69e2fe92a1c68c2c27c35f7dc5f.tar.gz ghdl-d646114db387b69e2fe92a1c68c2c27c35f7dc5f.tar.bz2 ghdl-d646114db387b69e2fe92a1c68c2c27c35f7dc5f.zip | |
elab-vhdl_values: factorize code
Diffstat (limited to 'src/simul/simul-vhdl_simul.adb')
| -rw-r--r-- | src/simul/simul-vhdl_simul.adb | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/simul/simul-vhdl_simul.adb b/src/simul/simul-vhdl_simul.adb index 856f18a0b..cd34a5ca4 100644 --- a/src/simul/simul-vhdl_simul.adb +++ b/src/simul/simul-vhdl_simul.adb @@ -1990,7 +1990,7 @@ package body Simul.Vhdl_Simul is end loop; -- Call resolution function - Res := Exec_Resolution_Call (R.Inst, R.Func, Create_Value_Memory (Arr)); + Res := Exec_Resolution_Call (R.Inst, R.Func, Create_Value_Memtyp (Arr)); -- Set driving value. Exec_Write_Signal (R.Sig, (Res.Typ, Res.Val.Mem), @@ -2338,7 +2338,7 @@ package body Simul.Vhdl_Simul is Res : Valtyp; begin Res := Exec_Resolution_Call (Inst, Get_Implementation (Func), - Create_Value_Memory (Val)); + Create_Value_Memtyp (Val)); Res := Synth.Vhdl_Expr.Synth_Subtype_Conversion (Inst, Res, Res_Typ, False, Func); if Res = No_Valtyp then |