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| author | Tristan Gingold <tgingold@free.fr> | 2023-01-11 05:02:53 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2023-01-11 05:02:53 +0100 |
| commit | 8b2a821eb457c200db22443ba0b562b94d0d90b5 (patch) | |
| tree | f72dd464fd2c9ee6f991af29a47452b117b2a276 /src/simul/simul-vhdl_simul.adb | |
| parent | 976b7863df71850e8a3e1b791d2c38907db397b3 (diff) | |
| download | ghdl-8b2a821eb457c200db22443ba0b562b94d0d90b5.tar.gz ghdl-8b2a821eb457c200db22443ba0b562b94d0d90b5.tar.bz2 ghdl-8b2a821eb457c200db22443ba0b562b94d0d90b5.zip | |
simul: add debug command 'run -s'
Diffstat (limited to 'src/simul/simul-vhdl_simul.adb')
| -rw-r--r-- | src/simul/simul-vhdl_simul.adb | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/src/simul/simul-vhdl_simul.adb b/src/simul/simul-vhdl_simul.adb index 82342b599..2a330d472 100644 --- a/src/simul/simul-vhdl_simul.adb +++ b/src/simul/simul-vhdl_simul.adb @@ -4040,6 +4040,7 @@ package body Simul.Vhdl_Simul is Status : Integer; begin Break_Time := Std_Time'Last; + Break_Step := False; Grt.Options.Progname := To_Ghdl_C_String (Ghdl_Progname'Address); Grt.Errors.Set_Error_Stream (Grt.Stdio.stdout); @@ -4092,11 +4093,13 @@ package body Simul.Vhdl_Simul is or Status = Grt.Errors.Run_Stop or Status = Grt.Errors.Run_Finished; - if Current_Time >= Break_Time - and then Break_Time /= Std_Time'Last + if Break_Step + or else (Current_Time >= Break_Time + and then Break_Time /= Std_Time'Last) then -- No not break anymore on time, Break_Time := Std_Time'Last; + Break_Step := False; Elab.Debugger.Debug_Time; end if; |