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| author | Tristan Gingold <tgingold@free.fr> | 2023-01-03 13:53:37 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2023-01-03 16:47:28 +0100 |
| commit | 1e5f96642bbf470934f245c98908337f75abb35a (patch) | |
| tree | 32c6a26b31a4e27e7306ac7c9faa7159d65010a9 /src/simul/simul-vhdl_simul.adb | |
| parent | d7ffe048ed623283655a11ffc5e75d6e5731f738 (diff) | |
| download | ghdl-1e5f96642bbf470934f245c98908337f75abb35a.tar.gz ghdl-1e5f96642bbf470934f245c98908337f75abb35a.tar.bz2 ghdl-1e5f96642bbf470934f245c98908337f75abb35a.zip | |
synth: introduce type_array_unbounded
Diffstat (limited to 'src/simul/simul-vhdl_simul.adb')
| -rw-r--r-- | src/simul/simul-vhdl_simul.adb | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/simul/simul-vhdl_simul.adb b/src/simul/simul-vhdl_simul.adb index 354ca062f..37fd14d69 100644 --- a/src/simul/simul-vhdl_simul.adb +++ b/src/simul/simul-vhdl_simul.adb @@ -2576,6 +2576,7 @@ package body Simul.Vhdl_Simul is when Type_Slice | Type_Access + | Type_Array_Unbounded | Type_Unbounded_Vector | Type_Unbounded_Array | Type_Unbounded_Record @@ -2739,6 +2740,7 @@ package body Simul.Vhdl_Simul is when Type_Slice | Type_Access + | Type_Array_Unbounded | Type_Unbounded_Vector | Type_Unbounded_Array | Type_Unbounded_Record |