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| author | Tristan Gingold <tgingold@free.fr> | 2022-09-17 16:36:34 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-09-17 19:03:27 +0200 |
| commit | 69ee33d1f0e4559b868068c955ef9c24f0438a11 (patch) | |
| tree | c6088f2f334bc1650536e245b6270ba7afbbccbb /src/simul/simul-vhdl_elab.adb | |
| parent | 6e800dc93b88801fcb9465cb3ca95b14e8489200 (diff) | |
| download | ghdl-69ee33d1f0e4559b868068c955ef9c24f0438a11.tar.gz ghdl-69ee33d1f0e4559b868068c955ef9c24f0438a11.tar.bz2 ghdl-69ee33d1f0e4559b868068c955ef9c24f0438a11.zip | |
synth: factorize code (reuse synth_constant_declaration)
Diffstat (limited to 'src/simul/simul-vhdl_elab.adb')
| -rw-r--r-- | src/simul/simul-vhdl_elab.adb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/simul/simul-vhdl_elab.adb b/src/simul/simul-vhdl_elab.adb index 9c89cfa81..68135502c 100644 --- a/src/simul/simul-vhdl_elab.adb +++ b/src/simul/simul-vhdl_elab.adb @@ -149,7 +149,7 @@ package body Simul.Vhdl_Elab is -- Set it to the default value. if Val.Val.Init /= null then - Copy_Memory (E.Val, Val.Val.Init.Mem, E.Typ.Sz); + Copy_Memory (E.Val, Get_Memory (Val.Val.Init), E.Typ.Sz); else Write_Value_Default (E.Val, E.Typ); end if; |