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| author | Tristan Gingold <tgingold@free.fr> | 2022-09-06 20:42:55 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-09-06 20:42:55 +0200 |
| commit | 5954723f26a0600e2f3f69de482c30e585e75ba2 (patch) | |
| tree | 53ff984f436022b09994b74abf67c5907aaaaf75 /src/simul/simul-vhdl_elab.adb | |
| parent | 0061426b03bd806424e813fc7065478a8791d1e7 (diff) | |
| download | ghdl-5954723f26a0600e2f3f69de482c30e585e75ba2.tar.gz ghdl-5954723f26a0600e2f3f69de482c30e585e75ba2.tar.bz2 ghdl-5954723f26a0600e2f3f69de482c30e585e75ba2.zip | |
synth: handle generics in blocks
Diffstat (limited to 'src/simul/simul-vhdl_elab.adb')
| -rw-r--r-- | src/simul/simul-vhdl_elab.adb | 20 |
1 files changed, 18 insertions, 2 deletions
diff --git a/src/simul/simul-vhdl_elab.adb b/src/simul/simul-vhdl_elab.adb index 2a254279c..1332b479b 100644 --- a/src/simul/simul-vhdl_elab.adb +++ b/src/simul/simul-vhdl_elab.adb @@ -740,8 +740,13 @@ package body Simul.Vhdl_Elab is declare Sub : constant Synth_Instance_Acc := Get_Sub_Instance (Inst, Stmt); + Hdr : constant Node := Get_Block_Header (Stmt); begin Gather_Processes_1 (Sub); + if Hdr /= Null_Node then + Gather_Connections (Sub, Get_Port_Chain (Hdr), + Inst, Get_Port_Map_Aspect_Chain (Hdr)); + end if; end; when Iir_Kinds_Concurrent_Signal_Assignment | Iir_Kind_Concurrent_Assertion_Statement @@ -813,8 +818,19 @@ package body Simul.Vhdl_Elab is Gather_Processes_1 (Comp_Inst); end if; end; - when Iir_Kind_Generate_Statement_Body - | Iir_Kind_Block_Statement => + when Iir_Kind_Block_Statement => + declare + Hdr : constant Node := Get_Block_Header (N); + begin + if Hdr /= Null_Node then + Gather_Processes_Decls (Inst, Get_Port_Chain (Hdr)); + end if; + Gather_Processes_Decls + (Inst, Get_Declaration_Chain (N)); + Gather_Processes_Stmts + (Inst, Get_Concurrent_Statement_Chain (N)); + end; + when Iir_Kind_Generate_Statement_Body => Gather_Processes_Decls (Inst, Get_Declaration_Chain (N)); Gather_Processes_Stmts |