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author | Tristan Gingold <tgingold@free.fr> | 2019-05-30 10:07:25 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-05-30 10:07:25 +0200 |
commit | f771391fd9c0a99e1652209a74c1687c77a7ab35 (patch) | |
tree | e7a995d52b7f61909294f2952d8b900ec1e1e1ee /src/ghdldrv | |
parent | 3bce793cfe3bcf88065acbd1365976782746f5a4 (diff) | |
download | ghdl-f771391fd9c0a99e1652209a74c1687c77a7ab35.tar.gz ghdl-f771391fd9c0a99e1652209a74c1687c77a7ab35.tar.bz2 ghdl-f771391fd9c0a99e1652209a74c1687c77a7ab35.zip |
vhdl: renames disp_vhdl to prints
Diffstat (limited to 'src/ghdldrv')
-rw-r--r-- | src/ghdldrv/ghdllocal.adb | 4 | ||||
-rw-r--r-- | src/ghdldrv/ghdlprint.adb | 12 |
2 files changed, 11 insertions, 5 deletions
diff --git a/src/ghdldrv/ghdllocal.adb b/src/ghdldrv/ghdllocal.adb index 3aee26250..3b4884acb 100644 --- a/src/ghdldrv/ghdllocal.adb +++ b/src/ghdldrv/ghdllocal.adb @@ -27,7 +27,7 @@ with Vhdl.Std_Package; with Flags; with Name_Table; with Std_Names; -with Vhdl.Disp_Vhdl; +with Vhdl.Prints; with Default_Paths; with Vhdl.Scanner; with Errorout; @@ -1118,7 +1118,7 @@ package body Ghdllocal is end if; Flags.Bootstrap := True; Libraries.Load_Std_Library; - Vhdl.Disp_Vhdl.Disp_Vhdl (Vhdl.Std_Package.Std_Standard_Unit); + Vhdl.Prints.Disp_Vhdl (Vhdl.Std_Package.Std_Standard_Unit); end Perform_Action; -- Command --find-top. diff --git a/src/ghdldrv/ghdlprint.adb b/src/ghdldrv/ghdlprint.adb index 91168c023..7d232c697 100644 --- a/src/ghdldrv/ghdlprint.adb +++ b/src/ghdldrv/ghdlprint.adb @@ -37,7 +37,7 @@ with Vhdl.Xrefs; with Vhdl.Sem_Lib; use Vhdl.Sem_Lib; with Ghdlmain; use Ghdlmain; with Ghdllocal; use Ghdllocal; -with Vhdl.Disp_Vhdl; +with Vhdl.Prints; with Vhdl.Elocations; package body Ghdlprint is @@ -1024,17 +1024,23 @@ package body Ghdlprint is end if; Unit := Get_First_Design_Unit (Design_File); + if Cmd.Flag_Sem then + Design_File := Null_Iir; + end if; while Unit /= Null_Iir loop if Cmd.Flag_Sem then -- Analyze the design unit. Vhdl.Sem_Lib.Finish_Compilation (Unit, True); + if Cmd.Flag_Sem and then Design_File = Null_Iir then + Design_File := Get_Design_File (Unit); + end if; end if; Next_Unit := Get_Chain (Unit); if Errorout.Nbr_Errors = 0 then - Vhdl.Disp_Vhdl.Disp_Vhdl (Unit); - Set_Chain (Unit, Null_Iir); + Vhdl.Prints.Disp_Vhdl (Unit); if Cmd.Flag_Sem then + Set_Chain (Unit, Null_Iir); Libraries.Add_Design_Unit_Into_Library (Unit); end if; end if; |