ghdldrv/: initial support for foreign modules

3 files changed, 25 insertions, 8 deletions

diff --git a/src/ghdldrv/ghdlcomp.adb b/src/ghdldrv/ghdlcomp.adb
index 26c4915b3..c62348752 100644
--- a/src/ghdldrv/ghdlcomp.adb
+++ b/src/ghdldrv/ghdlcomp.adb
@@ -217,7 +217,7 @@ package body Ghdlcomp is
       end if;
    end Compile_Analyze_Init;
 
-   procedure Compile_Load_File (File : String)
+   procedure Compile_Load_Vhdl_File (File : String)
    is
       Res : Iir_Design_File;
       Design : Iir;
@@ -236,7 +236,7 @@ package body Ghdlcomp is
          Libraries.Add_Design_Unit_Into_Library (Design);
          Design := Next_Design;
       end loop;
-   end Compile_Load_File;
+   end Compile_Load_Vhdl_File;
 
    function Compile_Analyze_File (File : String) return Iir
    is
@@ -390,7 +390,7 @@ package body Ghdlcomp is
                      end if;
                      Libraries.Load_Work_Library (True);
                   else
-                     Compile_Load_File (Arg);
+                     Compile_Load_Vhdl_File (Arg);
                   end if;
                end;
             end loop;
diff --git a/src/ghdldrv/ghdlcomp.ads b/src/ghdldrv/ghdlcomp.ads
index fa26ee3b8..75d1e9f1d 100644
--- a/src/ghdldrv/ghdlcomp.ads
+++ b/src/ghdldrv/ghdlcomp.ads
@@ -97,11 +97,18 @@ package Ghdlcomp is
 
    --  Load and parse FILE, put library units in the work library (without
    --  analyzing them).
-   procedure Compile_Load_File (File : String);
+   procedure Compile_Load_Vhdl_File (File : String);
 
    --  Load, parse and analyze FILE.
    function Compile_Analyze_File (File : String) return Iir;
 
    procedure Compile_Elaborate (Unit_Name : String_Access);
    procedure Compile_Run;
+
+   --  Load and parse file (without analysis).  Put units in the work library.
+   type Load_File_Acc is access procedure (File : String);
+
+   --  Hook for verilog.
+   Init_Verilog_Options : Compile_Init_Acc;
+   Load_Verilog_File : Load_File_Acc;
 end Ghdlcomp;
diff --git a/src/ghdldrv/ghdlsynth.adb b/src/ghdldrv/ghdlsynth.adb
index c3101fc16..8a21169bc 100644
--- a/src/ghdldrv/ghdlsynth.adb
+++ b/src/ghdldrv/ghdlsynth.adb
@@ -277,6 +277,10 @@ package body Ghdlsynth is
          --  Do not create concurrent signal assignment for inertial
          --  association.  They are handled directly.
          Vhdl.Canon.Canon_Flag_Inertial_Associations := False;
+
+         if Ghdlcomp.Init_Verilog_Options /= null then
+            Ghdlcomp.Init_Verilog_Options.all (False);
+         end if;
       end if;
 
       --  Mark vendor libraries.
@@ -315,15 +319,21 @@ package body Ghdlsynth is
                case Files_Map.Find_Language (Arg) is
                   when Language_Vhdl
                     | Language_Psl =>
-                     null;
+                     Ghdlcomp.Compile_Load_Vhdl_File (Arg);
+                  when Language_Verilog =>
+                     if Ghdlcomp.Load_Verilog_File = null then
+                        Error_Msg_Option
+                          ("verilog file %i is not supported",
+                           (1 => +Name_Table.Get_Identifier (Arg)));
+                     else
+                        Ghdlcomp.Load_Verilog_File (Arg);
+                     end if;
                   when others =>
                      Errorout.Report_Msg
                        (Warnid_Library, Option, No_Source_Coord,
-                        "unexpected extension for vhdl file %i",
+                        "unexpected extension for file %i",
                         (1 => +Name_Table.Get_Identifier (Arg)));
                end case;
-
-               Ghdlcomp.Compile_Load_File (Arg);
             end if;
          end;
       end loop;