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| author | Tristan Gingold <tgingold@free.fr> | 2022-09-25 15:15:48 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-09-25 15:15:48 +0200 |
| commit | 551fe31c9a9331998199369f903ede9c3cb4a79c (patch) | |
| tree | a0eaa704100872c10430e05981be137b3dc70bab /src/ghdldrv | |
| parent | 8e56ee72b5095412f0de3d358668f41579c1194e (diff) | |
| download | ghdl-551fe31c9a9331998199369f903ede9c3cb4a79c.tar.gz ghdl-551fe31c9a9331998199369f903ede9c3cb4a79c.tar.bz2 ghdl-551fe31c9a9331998199369f903ede9c3cb4a79c.zip | |
synth: rework error procedure, always pass the instance
Diffstat (limited to 'src/ghdldrv')
| -rw-r--r-- | src/ghdldrv/ghdlsimul.adb | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/ghdldrv/ghdlsimul.adb b/src/ghdldrv/ghdlsimul.adb index 6a6140cee..0a752dc22 100644 --- a/src/ghdldrv/ghdlsimul.adb +++ b/src/ghdldrv/ghdlsimul.adb @@ -47,6 +47,7 @@ with Elab.Vhdl_Insts; with Elab.Debugger; with Synth.Flags; +with Synth.Errors; with Simul.Vhdl_Elab; with Simul.Vhdl_Simul; @@ -88,6 +89,7 @@ package body Ghdlsimul is end loop; Synth.Flags.Flag_Simulation := True; + Synth.Errors.Debug_Handler := Elab.Debugger.Debug_Error'Access; Lib_Unit := Get_Library_Unit (Config); pragma Assert (Get_Kind (Lib_Unit) /= Iir_Kind_Foreign_Module); |