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| author | Tristan Gingold <tgingold@free.fr> | 2019-10-11 06:35:48 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-10-11 06:35:48 +0200 |
| commit | bca8844670a1a13964f42dc4223f720c4f405939 (patch) | |
| tree | faea5ea7788fe501195c0539969f9c90aee06564 /python | |
| parent | 2714a30c3753c76cda95eb994851a8be95e60ad9 (diff) | |
| download | ghdl-bca8844670a1a13964f42dc4223f720c4f405939.tar.gz ghdl-bca8844670a1a13964f42dc4223f720c4f405939.tar.bz2 ghdl-bca8844670a1a13964f42dc4223f720c4f405939.zip | |
vhdl: recognize std_logic_signed package (from synopsys).
Diffstat (limited to 'python')
| -rw-r--r-- | python/libghdl/thin/std_names.py | 4 | ||||
| -rw-r--r-- | python/libghdl/thin/vhdl/nodes.py | 18 |
2 files changed, 16 insertions, 6 deletions
diff --git a/python/libghdl/thin/std_names.py b/python/libghdl/thin/std_names.py index c2ddef117..e9b7308b7 100644 --- a/python/libghdl/thin/std_names.py +++ b/python/libghdl/thin/std_names.py @@ -583,8 +583,8 @@ class Name: Unresolved_Signed = 797 Std_Logic_Arith = 798 Std_Logic_Signed = 799 - Std_Logic_Textio = 800 - Std_Logic_Unsigned = 801 + Std_Logic_Unsigned = 800 + Std_Logic_Textio = 801 To_Integer = 802 To_Unsigned = 803 To_Signed = 804 diff --git a/python/libghdl/thin/vhdl/nodes.py b/python/libghdl/thin/vhdl/nodes.py index d684700a6..b77434aa7 100644 --- a/python/libghdl/thin/vhdl/nodes.py +++ b/python/libghdl/thin/vhdl/nodes.py @@ -1199,10 +1199,20 @@ class Iir_Predefined: Ieee_Std_Logic_Unsigned_Ne_Slv_Slv = 320 Ieee_Std_Logic_Unsigned_Ne_Slv_Int = 321 Ieee_Std_Logic_Unsigned_Ne_Int_Slv = 322 - Ieee_Std_Logic_Arith_Conv_Unsigned_Int = 323 - Ieee_Std_Logic_Arith_Conv_Unsigned_Uns = 324 - Ieee_Std_Logic_Arith_Conv_Unsigned_Sgn = 325 - Ieee_Std_Logic_Arith_Conv_Unsigned_Log = 326 + Ieee_Std_Logic_Signed_Add_Slv_Slv = 323 + Ieee_Std_Logic_Signed_Add_Slv_Int = 324 + Ieee_Std_Logic_Signed_Add_Int_Slv = 325 + Ieee_Std_Logic_Signed_Add_Slv_Sl = 326 + Ieee_Std_Logic_Signed_Add_Sl_Slv = 327 + Ieee_Std_Logic_Signed_Sub_Slv_Slv = 328 + Ieee_Std_Logic_Signed_Sub_Slv_Int = 329 + Ieee_Std_Logic_Signed_Sub_Int_Slv = 330 + Ieee_Std_Logic_Signed_Sub_Slv_Sl = 331 + Ieee_Std_Logic_Signed_Sub_Sl_Slv = 332 + Ieee_Std_Logic_Arith_Conv_Unsigned_Int = 333 + Ieee_Std_Logic_Arith_Conv_Unsigned_Uns = 334 + Ieee_Std_Logic_Arith_Conv_Unsigned_Sgn = 335 + Ieee_Std_Logic_Arith_Conv_Unsigned_Log = 336 Get_Kind = libghdl.vhdl__nodes__get_kind Get_Location = libghdl.vhdl__nodes__get_location |