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| author | Tristan Gingold <tgingold@free.fr> | 2019-10-12 07:07:42 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-10-13 18:54:22 +0200 |
| commit | b513a6170db4fe14eb6e885e859445d763633266 (patch) | |
| tree | 5c9339dd6eb0183c678beacb12ebd00c9abd3414 /python | |
| parent | f7300b2906b6c918c83b6037d7223e7409dd440e (diff) | |
| download | ghdl-b513a6170db4fe14eb6e885e859445d763633266.tar.gz ghdl-b513a6170db4fe14eb6e885e859445d763633266.tar.bz2 ghdl-b513a6170db4fe14eb6e885e859445d763633266.zip | |
vhdl: recognize std_logic_unsigned.conv_integer.
Handle more operators in synth.
Diffstat (limited to 'python')
| -rw-r--r-- | python/libghdl/thin/vhdl/nodes.py | 37 |
1 files changed, 19 insertions, 18 deletions
diff --git a/python/libghdl/thin/vhdl/nodes.py b/python/libghdl/thin/vhdl/nodes.py index 700846bbb..43ca5fee3 100644 --- a/python/libghdl/thin/vhdl/nodes.py +++ b/python/libghdl/thin/vhdl/nodes.py @@ -1199,24 +1199,25 @@ class Iir_Predefined: Ieee_Std_Logic_Unsigned_Ne_Slv_Slv = 320 Ieee_Std_Logic_Unsigned_Ne_Slv_Int = 321 Ieee_Std_Logic_Unsigned_Ne_Int_Slv = 322 - Ieee_Std_Logic_Signed_Add_Slv_Slv = 323 - Ieee_Std_Logic_Signed_Add_Slv_Int = 324 - Ieee_Std_Logic_Signed_Add_Int_Slv = 325 - Ieee_Std_Logic_Signed_Add_Slv_Sl = 326 - Ieee_Std_Logic_Signed_Add_Sl_Slv = 327 - Ieee_Std_Logic_Signed_Sub_Slv_Slv = 328 - Ieee_Std_Logic_Signed_Sub_Slv_Int = 329 - Ieee_Std_Logic_Signed_Sub_Int_Slv = 330 - Ieee_Std_Logic_Signed_Sub_Slv_Sl = 331 - Ieee_Std_Logic_Signed_Sub_Sl_Slv = 332 - Ieee_Std_Logic_Arith_Conv_Unsigned_Int = 333 - Ieee_Std_Logic_Arith_Conv_Unsigned_Uns = 334 - Ieee_Std_Logic_Arith_Conv_Unsigned_Sgn = 335 - Ieee_Std_Logic_Arith_Conv_Unsigned_Log = 336 - Ieee_Std_Logic_Arith_Conv_Integer_Int = 337 - Ieee_Std_Logic_Arith_Conv_Integer_Uns = 338 - Ieee_Std_Logic_Arith_Conv_Integer_Sgn = 339 - Ieee_Std_Logic_Arith_Conv_Integer_Log = 340 + Ieee_Std_Logic_Unsigned_Conv_Integer = 323 + Ieee_Std_Logic_Signed_Add_Slv_Slv = 324 + Ieee_Std_Logic_Signed_Add_Slv_Int = 325 + Ieee_Std_Logic_Signed_Add_Int_Slv = 326 + Ieee_Std_Logic_Signed_Add_Slv_Sl = 327 + Ieee_Std_Logic_Signed_Add_Sl_Slv = 328 + Ieee_Std_Logic_Signed_Sub_Slv_Slv = 329 + Ieee_Std_Logic_Signed_Sub_Slv_Int = 330 + Ieee_Std_Logic_Signed_Sub_Int_Slv = 331 + Ieee_Std_Logic_Signed_Sub_Slv_Sl = 332 + Ieee_Std_Logic_Signed_Sub_Sl_Slv = 333 + Ieee_Std_Logic_Arith_Conv_Unsigned_Int = 334 + Ieee_Std_Logic_Arith_Conv_Unsigned_Uns = 335 + Ieee_Std_Logic_Arith_Conv_Unsigned_Sgn = 336 + Ieee_Std_Logic_Arith_Conv_Unsigned_Log = 337 + Ieee_Std_Logic_Arith_Conv_Integer_Int = 338 + Ieee_Std_Logic_Arith_Conv_Integer_Uns = 339 + Ieee_Std_Logic_Arith_Conv_Integer_Sgn = 340 + Ieee_Std_Logic_Arith_Conv_Integer_Log = 341 Get_Kind = libghdl.vhdl__nodes__get_kind Get_Location = libghdl.vhdl__nodes__get_location |