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author | Tristan Gingold <tgingold@free.fr> | 2020-08-01 07:36:43 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2020-08-01 07:36:43 +0200 |
commit | a358d58e8592316fa1421445e73531e00247744f (patch) | |
tree | 9f1d2580d13feaeb3d6d4e3aa8cea53a9b4c3cfd /python/libghdl/thin/std_names.py | |
parent | c428e1f4c697d550a8e986aa2c1918a992826234 (diff) | |
download | ghdl-a358d58e8592316fa1421445e73531e00247744f.tar.gz ghdl-a358d58e8592316fa1421445e73531e00247744f.tar.bz2 ghdl-a358d58e8592316fa1421445e73531e00247744f.zip |
vhdl: add force and release tokens. For #1416
Diffstat (limited to 'python/libghdl/thin/std_names.py')
-rw-r--r-- | python/libghdl/thin/std_names.py | 144 |
1 files changed, 72 insertions, 72 deletions
diff --git a/python/libghdl/thin/std_names.py b/python/libghdl/thin/std_names.py index ba1686a9e..f7bd4fef6 100644 --- a/python/libghdl/thin/std_names.py +++ b/python/libghdl/thin/std_names.py @@ -107,78 +107,78 @@ class Name: Context = 356 Cover = 357 Default = 358 - Parameter = 359 - Property = 360 - Restrict = 361 - Restrict_Guarantee = 362 - Sequence = 363 - Vmode = 364 - Vprop = 365 - Vunit = 366 - Last_Vhdl08 = 366 - First_Ams_Keyword = 367 - Across = 367 - Break = 368 - Limit = 369 - Nature = 370 - Noise = 371 - Procedural = 372 - Quantity = 373 - Reference = 374 - Spectrum = 375 - Subnature = 376 - Terminal = 377 - Through = 378 - Tolerance = 379 - Last_AMS_Vhdl = 379 - Last_Keyword = 379 - First_Verilog = 380 - Always = 380 - Assign = 381 - Buf = 382 - Bufif0 = 383 - Bufif1 = 384 - Casex = 385 - Casez = 386 - Cmos = 387 - Deassign = 388 - Defparam = 389 - Disable = 390 - Edge = 391 - Endcase = 392 - Endfunction = 393 - Endmodule = 394 - Endprimitive = 395 - Endspecify = 396 - Endtable = 397 - Endtask = 398 - Force = 399 - Forever = 400 - Fork = 401 - Highz0 = 402 - Highz1 = 403 - Ifnone = 404 - Initial = 405 - Input = 406 - Join = 407 - Large = 408 - Macromodule = 409 - Medium = 410 - Module = 411 - Negedge = 412 - Nmos = 413 - Notif0 = 414 - Notif1 = 415 - Output = 416 - Pmos = 417 - Posedge = 418 - Primitive = 419 - Pull0 = 420 - Pull1 = 421 - Pulldown = 422 - Pullup = 423 - Realtime = 424 - Release = 425 + Force = 359 + Parameter = 360 + Property = 361 + Release = 362 + Restrict = 363 + Restrict_Guarantee = 364 + Sequence = 365 + Vmode = 366 + Vprop = 367 + Vunit = 368 + Last_Vhdl08 = 368 + First_Ams_Keyword = 369 + Across = 369 + Break = 370 + Limit = 371 + Nature = 372 + Noise = 373 + Procedural = 374 + Quantity = 375 + Reference = 376 + Spectrum = 377 + Subnature = 378 + Terminal = 379 + Through = 380 + Tolerance = 381 + Last_AMS_Vhdl = 381 + Last_Keyword = 381 + First_Verilog = 382 + Always = 382 + Assign = 383 + Buf = 384 + Bufif0 = 385 + Bufif1 = 386 + Casex = 387 + Casez = 388 + Cmos = 389 + Deassign = 390 + Defparam = 391 + Disable = 392 + Edge = 393 + Endcase = 394 + Endfunction = 395 + Endmodule = 396 + Endprimitive = 397 + Endspecify = 398 + Endtable = 399 + Endtask = 400 + Forever = 401 + Fork = 402 + Highz0 = 403 + Highz1 = 404 + Ifnone = 405 + Initial = 406 + Input = 407 + Join = 408 + Large = 409 + Macromodule = 410 + Medium = 411 + Module = 412 + Negedge = 413 + Nmos = 414 + Notif0 = 415 + Notif1 = 416 + Output = 417 + Pmos = 418 + Posedge = 419 + Primitive = 420 + Pull0 = 421 + Pull1 = 422 + Pulldown = 423 + Pullup = 424 + Realtime = 425 Reg = 426 Repeat = 427 Rcmos = 428 |