Mode code more local.

(cherry picked from commit 2e64bb94806f080e015a5aea38c7c8734b971377)

6 files changed, 149 insertions, 91 deletions

diff --git a/pyGHDL/dom/DesignUnit.py b/pyGHDL/dom/DesignUnit.py
index dee86cab3..3619c47c5 100644
--- a/pyGHDL/dom/DesignUnit.py
+++ b/pyGHDL/dom/DesignUnit.py
@@ -48,19 +48,16 @@ from pyVHDLModel.VHDLModel import PackageBody as VHDLModel_PackageBody
 from pyVHDLModel.VHDLModel import Context as VHDLModel_Context
 from pyVHDLModel.VHDLModel import Configuration as VHDLModel_Configuration
 
-from pyGHDL.libghdl import utils
 from pyGHDL.libghdl.vhdl import nodes
 
-from pyGHDL.dom._Utils import NodeToName, GetIirKindOfNode
+from pyGHDL.dom._Utils import NodeToName
 from pyGHDL.dom._Translate import (
-    GetExpressionFromNode,
-    GetSubtypeIndicationFromNode,
     GetGenericsFromChainedNodes,
     GetPortsFromChainedNodes,
     GetDeclaredItemsFromChainedNodes,
 )
-from pyGHDL.dom.Common import GHDLMixin, DOMException
-from pyGHDL.dom.Object import Constant, Signal
+from pyGHDL.dom.Common import GHDLMixin
+
 
 __all__ = []
 
diff --git a/pyGHDL/dom/Expression.py b/pyGHDL/dom/Expression.py
index 754b73304..80ef2823c 100644
--- a/pyGHDL/dom/Expression.py
+++ b/pyGHDL/dom/Expression.py
@@ -30,6 +30,7 @@
 #
 # SPDX-License-Identifier: GPL-2.0-or-later
 # ============================================================================
+from pyGHDL.libghdl.vhdl import nodes
 from pydecor import export
 
 from pyVHDLModel.VHDLModel import (
@@ -71,29 +72,48 @@ from pyVHDLModel.VHDLModel import (
 __all__ = []
 
 
+class _ParseUnaryExpression:
+    @classmethod
+    def parse(cls, node):
+        from pyGHDL.dom._Translate import GetExpressionFromNode
+
+        operand = GetExpressionFromNode(nodes.Get_Operand(node))
+        return cls(operand)
+
+
+class _ParseBinaryExpression:
+    @classmethod
+    def parse(cls, node):
+        from pyGHDL.dom._Translate import GetExpressionFromNode
+
+        left = GetExpressionFromNode(nodes.Get_Left(node))
+        right = GetExpressionFromNode(nodes.Get_Right(node))
+        return cls(left, right)
+
+
 @export
-class InverseExpression(VHDLModel_InverseExpression):
+class InverseExpression(VHDLModel_InverseExpression, _ParseUnaryExpression):
     def __init__(self, operand: Expression):
         super().__init__()
         self._operand = operand
 
 
 @export
-class IdentityExpression(VHDLModel_IdentityExpression):
+class IdentityExpression(VHDLModel_IdentityExpression, _ParseUnaryExpression):
     def __init__(self, operand: Expression):
         super().__init__()
         self._operand = operand
 
 
 @export
-class NegationExpression(VHDLModel_NegationExpression):
+class NegationExpression(VHDLModel_NegationExpression, _ParseUnaryExpression):
     def __init__(self, operand: Expression):
         super().__init__()
         self._operand = operand
 
 
 @export
-class AbsoluteExpression(VHDLModel_AbsoluteExpression):
+class AbsoluteExpression(VHDLModel_AbsoluteExpression, _ParseUnaryExpression):
     def __init__(self, operand: Expression):
         super().__init__()
         self._operand = operand
@@ -121,7 +141,7 @@ class QualifiedExpression(VHDLModel_QualifiedExpression):
 
 
 @export
-class AdditionExpression(VHDLModel_AdditionExpression):
+class AdditionExpression(VHDLModel_AdditionExpression, _ParseBinaryExpression):
     def __init__(self, left: Expression, right: Expression):
         super().__init__()
         self._leftOperand = left
@@ -129,7 +149,7 @@ class AdditionExpression(VHDLModel_AdditionExpression):
 
 
 @export
-class SubtractionExpression(VHDLModel_SubtractionExpression):
+class SubtractionExpression(VHDLModel_SubtractionExpression, _ParseBinaryExpression):
     def __init__(self, left: Expression, right: Expression):
         super().__init__()
         self._leftOperand = left
@@ -137,7 +157,9 @@ class SubtractionExpression(VHDLModel_SubtractionExpression):
 
 
 @export
-class ConcatenationExpression(VHDLModel_ConcatenationExpression):
+class ConcatenationExpression(
+    VHDLModel_ConcatenationExpression, _ParseBinaryExpression
+):
     def __init__(self, left: Expression, right: Expression):
         super().__init__()
         self._leftOperand = left
@@ -145,7 +167,7 @@ class ConcatenationExpression(VHDLModel_ConcatenationExpression):
 
 
 @export
-class MultiplyExpression(VHDLModel_MultiplyExpression):
+class MultiplyExpression(VHDLModel_MultiplyExpression, _ParseBinaryExpression):
     def __init__(self, left: Expression, right: Expression):
         super().__init__()
         self._leftOperand = left
@@ -153,7 +175,7 @@ class MultiplyExpression(VHDLModel_MultiplyExpression):
 
 
 @export
-class DivisionExpression(VHDLModel_DivisionExpression):
+class DivisionExpression(VHDLModel_DivisionExpression, _ParseBinaryExpression):
     def __init__(self, left: Expression, right: Expression):
         super().__init__()
         self._leftOperand = left
@@ -161,7 +183,7 @@ class DivisionExpression(VHDLModel_DivisionExpression):
 
 
 @export
-class RemainderExpression(VHDLModel_RemainderExpression):
+class RemainderExpression(VHDLModel_RemainderExpression, _ParseBinaryExpression):
     def __init__(self, left: Expression, right: Expression):
         super().__init__()
         self._leftOperand = left
@@ -169,7 +191,7 @@ class RemainderExpression(VHDLModel_RemainderExpression):
 
 
 @export
-class ModuloExpression(VHDLModel_ModuloExpression):
+class ModuloExpression(VHDLModel_ModuloExpression, _ParseBinaryExpression):
     def __init__(self, left: Expression, right: Expression):
         super().__init__()
         self._leftOperand = left
@@ -177,7 +199,9 @@ class ModuloExpression(VHDLModel_ModuloExpression):
 
 
 @export
-class ExponentiationExpression(VHDLModel_ExponentiationExpression):
+class ExponentiationExpression(
+    VHDLModel_ExponentiationExpression, _ParseBinaryExpression
+):
     def __init__(self, left: Expression, right: Expression):
         super().__init__()
         self._leftOperand = left
@@ -185,7 +209,7 @@ class ExponentiationExpression(VHDLModel_ExponentiationExpression):
 
 
 @export
-class AndExpression(VHDLModel_AndExpression):
+class AndExpression(VHDLModel_AndExpression, _ParseBinaryExpression):
     def __init__(self, left: Expression, right: Expression):
         super().__init__()
         self._leftOperand = left
@@ -193,7 +217,7 @@ class AndExpression(VHDLModel_AndExpression):
 
 
 @export
-class NandExpression(VHDLModel_NandExpression):
+class NandExpression(VHDLModel_NandExpression, _ParseBinaryExpression):
     def __init__(self, left: Expression, right: Expression):
         super().__init__()
         self._leftOperand = left
@@ -201,7 +225,7 @@ class NandExpression(VHDLModel_NandExpression):
 
 
 @export
-class OrExpression(VHDLModel_OrExpression):
+class OrExpression(VHDLModel_OrExpression, _ParseBinaryExpression):
     def __init__(self, left: Expression, right: Expression):
         super().__init__()
         self._leftOperand = left
@@ -209,7 +233,7 @@ class OrExpression(VHDLModel_OrExpression):
 
 
 @export
-class NorExpression(VHDLModel_NorExpression):
+class NorExpression(VHDLModel_NorExpression, _ParseBinaryExpression):
     def __init__(self, left: Expression, right: Expression):
         super().__init__()
         self._leftOperand = left
@@ -217,7 +241,7 @@ class NorExpression(VHDLModel_NorExpression):
 
 
 @export
-class XorExpression(VHDLModel_XorExpression):
+class XorExpression(VHDLModel_XorExpression, _ParseBinaryExpression):
     def __init__(self, left: Expression, right: Expression):
         super().__init__()
         self._leftOperand = left
@@ -225,7 +249,7 @@ class XorExpression(VHDLModel_XorExpression):
 
 
 @export
-class XnorExpression(VHDLModel_XnorExpression):
+class XnorExpression(VHDLModel_XnorExpression, _ParseBinaryExpression):
     def __init__(self, left: Expression, right: Expression):
         super().__init__()
         self._leftOperand = left
@@ -233,7 +257,7 @@ class XnorExpression(VHDLModel_XnorExpression):
 
 
 @export
-class EqualExpression(VHDLModel_EqualExpression):
+class EqualExpression(VHDLModel_EqualExpression, _ParseBinaryExpression):
     def __init__(self, left: Expression, right: Expression):
         super().__init__()
         self._leftOperand = left
@@ -241,7 +265,7 @@ class EqualExpression(VHDLModel_EqualExpression):
 
 
 @export
-class UnequalExpression(VHDLModel_UnequalExpression):
+class UnequalExpression(VHDLModel_UnequalExpression, _ParseBinaryExpression):
     def __init__(self, left: Expression, right: Expression):
         super().__init__()
         self._leftOperand = left
@@ -249,7 +273,7 @@ class UnequalExpression(VHDLModel_UnequalExpression):
 
 
 @export
-class GreaterThanExpression(VHDLModel_GreaterThanExpression):
+class GreaterThanExpression(VHDLModel_GreaterThanExpression, _ParseBinaryExpression):
     def __init__(self, left: Expression, right: Expression):
         super().__init__()
         self._leftOperand = left
@@ -257,7 +281,7 @@ class GreaterThanExpression(VHDLModel_GreaterThanExpression):
 
 
 @export
-class GreaterEqualExpression(VHDLModel_GreaterEqualExpression):
+class GreaterEqualExpression(VHDLModel_GreaterEqualExpression, _ParseBinaryExpression):
     def __init__(self, left: Expression, right: Expression):
         super().__init__()
         self._leftOperand = left
@@ -265,7 +289,7 @@ class GreaterEqualExpression(VHDLModel_GreaterEqualExpression):
 
 
 @export
-class LessThanExpression(VHDLModel_LessThanExpression):
+class LessThanExpression(VHDLModel_LessThanExpression, _ParseBinaryExpression):
     def __init__(self, left: Expression, right: Expression):
         super().__init__()
         self._leftOperand = left
@@ -273,7 +297,9 @@ class LessThanExpression(VHDLModel_LessThanExpression):
 
 
 @export
-class ShiftRightLogicExpression(VHDLModel_ShiftRightLogicExpression):
+class ShiftRightLogicExpression(
+    VHDLModel_ShiftRightLogicExpression, _ParseBinaryExpression
+):
     def __init__(self, left: Expression, right: Expression):
         super().__init__()
         self._leftOperand = left
@@ -281,7 +307,9 @@ class ShiftRightLogicExpression(VHDLModel_ShiftRightLogicExpression):
 
 
 @export
-class ShiftLeftLogicExpression(VHDLModel_ShiftLeftLogicExpression):
+class ShiftLeftLogicExpression(
+    VHDLModel_ShiftLeftLogicExpression, _ParseBinaryExpression
+):
     def __init__(self, left: Expression, right: Expression):
         super().__init__()
         self._leftOperand = left
@@ -289,7 +317,9 @@ class ShiftLeftLogicExpression(VHDLModel_ShiftLeftLogicExpression):
 
 
 @export
-class ShiftRightArithmeticExpression(VHDLModel_ShiftRightArithmeticExpression):
+class ShiftRightArithmeticExpression(
+    VHDLModel_ShiftRightArithmeticExpression, _ParseBinaryExpression
+):
     def __init__(self, left: Expression, right: Expression):
         super().__init__()
         self._leftOperand = left
@@ -297,7 +327,9 @@ class ShiftRightArithmeticExpression(VHDLModel_ShiftRightArithmeticExpression):
 
 
 @export
-class ShiftLeftArithmeticExpression(VHDLModel_ShiftLeftArithmeticExpression):
+class ShiftLeftArithmeticExpression(
+    VHDLModel_ShiftLeftArithmeticExpression, _ParseBinaryExpression
+):
     def __init__(self, left: Expression, right: Expression):
         super().__init__()
         self._leftOperand = left
@@ -305,7 +337,7 @@ class ShiftLeftArithmeticExpression(VHDLModel_ShiftLeftArithmeticExpression):
 
 
 @export
-class RotateRightExpression(VHDLModel_RotateRightExpression):
+class RotateRightExpression(VHDLModel_RotateRightExpression, _ParseBinaryExpression):
     def __init__(self, left: Expression, right: Expression):
         super().__init__()
         self._leftOperand = left
@@ -313,7 +345,7 @@ class RotateRightExpression(VHDLModel_RotateRightExpression):
 
 
 @export
-class RotateLeftExpression(VHDLModel_RotateLeftExpression):
+class RotateLeftExpression(VHDLModel_RotateLeftExpression, _ParseBinaryExpression):
     def __init__(self, left: Expression, right: Expression):
         super().__init__()
         self._leftOperand = left
diff --git a/pyGHDL/dom/Literal.py b/pyGHDL/dom/Literal.py
index 562b188fd..7c722583b 100644
--- a/pyGHDL/dom/Literal.py
+++ b/pyGHDL/dom/Literal.py
@@ -30,6 +30,9 @@
 #
 # SPDX-License-Identifier: GPL-2.0-or-later
 # ============================================================================
+from pyGHDL.libghdl import name_table
+
+from pyGHDL.libghdl.vhdl import nodes
 from pydecor import export
 
 from pyVHDLModel.VHDLModel import (
@@ -43,14 +46,24 @@ __all__ = []
 
 @export
 class IntegerLiteral(VHDLModel_IntegerLiteral):
-    pass
+    @classmethod
+    def parse(cls, node):
+        value = nodes.Get_Value(node)
+        return cls(value)
 
 
 @export
 class FloatingPointLiteral(VHDLModel_FloatingPointLiteral):
-    pass
+    @classmethod
+    def parse(cls, node):
+        value = nodes.Get_Fp_Value(node)
+        return cls(value)
 
 
 @export
 class CharacterLiteral(VHDLModel_CharacterLiteral):
-    pass
+    @classmethod
+    def parse(cls, node):
+        identifier = nodes.Get_Identifier(node)
+        value = name_table.Get_Character(identifier)
+        return cls(value)
diff --git a/pyGHDL/dom/Object.py b/pyGHDL/dom/Object.py
index f719cbed5..a6d62e658 100644
--- a/pyGHDL/dom/Object.py
+++ b/pyGHDL/dom/Object.py
@@ -30,8 +30,11 @@
 #
 # SPDX-License-Identifier: GPL-2.0-or-later
 # ============================================================================
+from pyGHDL.libghdl.vhdl import nodes
 from pydecor import export
 
+from pyGHDL.dom._Translate import GetSubtypeIndicationFromNode, GetExpressionFromNode
+from pyGHDL.dom._Utils import NodeToName
 from pyVHDLModel.VHDLModel import (
     Constant as VHDLModel_Constant,
     Variable as VHDLModel_Variable,
@@ -54,6 +57,16 @@ class Constant(VHDLModel_Constant):
         self._subType = subType
         self._defaultExpression = defaultExpression
 
+    @classmethod
+    def parse(cls, node):
+        name = NodeToName(node)
+        subTypeIndication = GetSubtypeIndicationFromNode(node, "constant", name)
+        defaultExpression = GetExpressionFromNode(nodes.Get_Default_Value(node))
+
+        constant = cls(name, subTypeIndication, defaultExpression)
+
+        return constant
+
 
 @export
 class Variable(VHDLModel_Variable):
@@ -66,6 +79,16 @@ class Variable(VHDLModel_Variable):
         self._subType = subType
         self._defaultExpression = defaultExpression
 
+    @classmethod
+    def parse(cls, node):
+        name = NodeToName(node)
+        subTypeIndication = GetSubtypeIndicationFromNode(node, "variable", name)
+        defaultExpression = GetExpressionFromNode(nodes.Get_Default_Value(node))
+
+        variable = cls(name, subTypeIndication, defaultExpression)
+
+        return variable
+
 
 @export
 class Signal(VHDLModel_Signal):
@@ -77,3 +100,13 @@ class Signal(VHDLModel_Signal):
         self._name = name
         self._subType = subType
         self._defaultExpression = defaultExpression
+
+    @classmethod
+    def parse(cls, node):
+        name = NodeToName(node)
+        subTypeIndication = GetSubtypeIndicationFromNode(node, "signal", name)
+        defaultExpression = GetExpressionFromNode(nodes.Get_Default_Value(node))
+
+        signal = cls(name, subTypeIndication, defaultExpression)
+
+        return signal
diff --git a/pyGHDL/dom/Symbol.py b/pyGHDL/dom/Symbol.py
index 09774a634..c7b681595 100644
--- a/pyGHDL/dom/Symbol.py
+++ b/pyGHDL/dom/Symbol.py
@@ -34,6 +34,7 @@ from pydecor import export
 
 from typing import List
 
+from pyGHDL.dom._Utils import NodeToName
 from pyVHDLModel.VHDLModel import (
     SimpleSubTypeSymbol as VHDLModel_SimpleSubTypeSymbol,
     ConstrainedSubTypeSymbol as VHDLModel_ConstrainedSubTypeSymbol,
@@ -49,14 +50,27 @@ class SimpleSubTypeSymbol(VHDLModel_SimpleSubTypeSymbol):
     def __init__(self, subTypeName: str):
         super().__init__(subTypeName=subTypeName)
 
+    @classmethod
+    def parse(cls, node):
+        pass
+
 
 @export
 class ConstrainedSubTypeSymbol(VHDLModel_ConstrainedSubTypeSymbol):
     def __init__(self, subTypeName: str, constraints: List[Constraint] = None):
         super().__init__(subTypeName=subTypeName, constraints=constraints)
 
+    @classmethod
+    def parse(cls, node):
+        pass
+
 
 @export
 class SimpleObjectSymbol(VHDLModel_SimpleObjectSymbol):
     def __init__(self, symbolName: str):
         super().__init__(symbolName)
+
+    @classmethod
+    def parse(cls, node):
+        name = NodeToName(node)
+        return cls(name)
diff --git a/pyGHDL/dom/_Translate.py b/pyGHDL/dom/_Translate.py
index 9435010ab..09cae55f9 100644
--- a/pyGHDL/dom/_Translate.py
+++ b/pyGHDL/dom/_Translate.py
@@ -91,53 +91,36 @@ def GetArrayConstraintsFromSubtypeIndication(subTypeIndication) -> List[Constrai
     return constraints
 
 
+__EXPRESSION_TRANSLATION = {
+    nodes.Iir_Kind.Simple_Name: SimpleObjectSymbol,
+    nodes.Iir_Kind.Integer_Literal: IntegerLiteral,
+    nodes.Iir_Kind.Floating_Point_Literal: FloatingPointLiteral,
+    nodes.Iir_Kind.Character_Literal: CharacterLiteral,
+    nodes.Iir_Kind.Negation_Operator: InverseExpression,
+    nodes.Iir_Kind.Addition_Operator: AdditionExpression,
+    nodes.Iir_Kind.Substraction_Operator: SubtractionExpression,
+    nodes.Iir_Kind.Multiplication_Operator: MultiplyExpression,
+    nodes.Iir_Kind.Division_Operator: DivisionExpression,
+    nodes.Iir_Kind.Exponentiation_Operator: ExponentiationExpression,
+    #    nodes.Iir_Kind.Aggregate: Aggregate
+}
+
+
 @export
 def GetExpressionFromNode(node) -> Expression:
     kind = GetIirKindOfNode(node)
 
-    if kind == nodes.Iir_Kind.Simple_Name:
-        name = NodeToName(node)
-        return SimpleObjectSymbol(name)
-    elif kind == nodes.Iir_Kind.Integer_Literal:
-        integerLiteralValue = nodes.Get_Value(node)
-        return IntegerLiteral(integerLiteralValue)
-    elif kind == nodes.Iir_Kind.Floating_Point_Literal:
-        fpLiteralValue = nodes.Get_Fp_Value(node)
-        return FloatingPointLiteral(fpLiteralValue)
-    elif kind == nodes.Iir_Kind.Character_Literal:
-        identifier = nodes.Get_Identifier(node)
-        characterLiteralValue = name_table.Get_Character(identifier)
-        return CharacterLiteral(characterLiteralValue)
-    elif kind == nodes.Iir_Kind.Negation_Operator:
-        operand = GetExpressionFromNode(nodes.Get_Operand(node))
-        return InverseExpression(operand)
-    elif kind == nodes.Iir_Kind.Addition_Operator:
-        left = GetExpressionFromNode(nodes.Get_Left(node))
-        right = GetExpressionFromNode(nodes.Get_Right(node))
-        return AdditionExpression(left, right)
-    elif kind == nodes.Iir_Kind.Substraction_Operator:
-        left = GetExpressionFromNode(nodes.Get_Left(node))
-        right = GetExpressionFromNode(nodes.Get_Right(node))
-        return SubtractionExpression(left, right)
-    elif kind == nodes.Iir_Kind.Multiplication_Operator:
-        left = GetExpressionFromNode(nodes.Get_Left(node))
-        right = GetExpressionFromNode(nodes.Get_Right(node))
-        return MultiplyExpression(left, right)
-    elif kind == nodes.Iir_Kind.Division_Operator:
-        left = GetExpressionFromNode(nodes.Get_Left(node))
-        right = GetExpressionFromNode(nodes.Get_Right(node))
-        return DivisionExpression(left, right)
-    elif kind == nodes.Iir_Kind.Exponentiation_Operator:
-        left = GetExpressionFromNode(nodes.Get_Left(node))
-        right = GetExpressionFromNode(nodes.Get_Right(node))
-        return ExponentiationExpression(left, right)
-    else:
+    try:
+        cls = __EXPRESSION_TRANSLATION[kind]
+    except KeyError:
         raise DOMException(
             "Unknown expression kind '{kindName}'({kind}) in expression '{expr}'.".format(
                 kind=kind, kindName=kind.name, expr=node
             )
         )
 
+    return cls.parse(node)
+
 
 # FIXME: rewrite to generator
 @export
@@ -190,25 +173,11 @@ def GetDeclaredItemsFromChainedNodes(nodeChain, entity: str, name: str):
         if kind == nodes.Iir_Kind.Constant_Declaration:
             from pyGHDL.dom.Object import Constant
 
-            constantName = NodeToName(item)
-            subTypeIndication = GetSubtypeIndicationFromNode(
-                item, "constant", constantName
-            )
-            defaultExpression = GetExpressionFromNode(nodes.Get_Default_Value(item))
-
-            constant = Constant(constantName, subTypeIndication, defaultExpression)
-
-            result.append(constant)
+            result.append(Constant.parse(item))
         elif kind == nodes.Iir_Kind.Signal_Declaration:
             from pyGHDL.dom.Object import Signal
 
-            signalName = NodeToName(item)
-            subTypeIndication = GetSubtypeIndicationFromNode(item, "signal", signalName)
-            defaultExpression = GetExpressionFromNode(nodes.Get_Default_Value(item))
-
-            constant = Signal(signalName, subTypeIndication, defaultExpression)
-
-            result.append(constant)
+            result.append(Signal.parse(item))
         elif kind == nodes.Iir_Kind.Anonymous_Type_Declaration:
             typeName = NodeToName(item)
             print("found type '{name}'".format(name=typeName))