Preparations for PSL.

3 files changed, 127 insertions, 2 deletions

diff --git a/pyGHDL/dom/DesignUnit.py b/pyGHDL/dom/DesignUnit.py
index 54816aef1..d5bf161fd 100644
--- a/pyGHDL/dom/DesignUnit.py
+++ b/pyGHDL/dom/DesignUnit.py
@@ -41,8 +41,6 @@ This module contains all DOM classes for VHDL's design units (:class:`context <E
 """
 from typing import List
 
-from pyGHDL.dom import DOMMixin
-from pyGHDL.libghdl._types import Iir
 from pydecor import export
 
 from pyVHDLModel.VHDLModel import (
@@ -62,7 +60,9 @@ from pyVHDLModel.VHDLModel import (
     ConcurrentStatement,
 )
 
+from pyGHDL.libghdl._types import Iir
 from pyGHDL.libghdl.vhdl import nodes
+from pyGHDL.dom import DOMMixin
 from pyGHDL.dom._Utils import GetNameOfNode
 from pyGHDL.dom._Translate import (
     GetGenericsFromChainedNodes,
diff --git a/pyGHDL/dom/NonStandard.py b/pyGHDL/dom/NonStandard.py
index 1524b549f..bf48db900 100644
--- a/pyGHDL/dom/NonStandard.py
+++ b/pyGHDL/dom/NonStandard.py
@@ -42,6 +42,7 @@ from typing import Any
 
 from pydecor import export
 
+from pyGHDL.dom.PSL import VerificationUnit, VerificationProperty, VerificationMode
 from pyVHDLModel.VHDLModel import (
     Design as VHDLModel_Design,
     Library as VHDLModel_Library,
@@ -198,6 +199,18 @@ class Document(VHDLModel_Document):
                 configuration = Configuration.parse(libraryUnit)
                 self.Configurations.append(configuration)
 
+            elif nodeKind == nodes.Iir_Kind.Vunit_Declaration:
+                vunit = VerificationUnit.parse(libraryUnit)
+                self.VerificationUnits.append(vunit)
+
+            elif nodeKind == nodes.Iir_Kind.Vprop_Declaration:
+                vprop = VerificationProperty.parse(libraryUnit)
+                self.VerificationProperties.append(vprop)
+
+            elif nodeKind == nodes.Iir_Kind.Vmode_Declaration:
+                vmod = VerificationMode.parse(libraryUnit)
+                self.VerificationModes.append(vmod)
+
             else:
                 raise DOMException(
                     "Unknown design unit kind '{kindName}'({kind}).".format(
diff --git a/pyGHDL/dom/PSL.py b/pyGHDL/dom/PSL.py
new file mode 100644
index 000000000..dd859e5b3
--- /dev/null
+++ b/pyGHDL/dom/PSL.py
@@ -0,0 +1,112 @@
+# =============================================================================
+#               ____ _   _ ____  _          _
+#  _ __  _   _ / ___| | | |  _ \| |      __| | ___  _ __ ___
+# | '_ \| | | | |  _| |_| | | | | |     / _` |/ _ \| '_ ` _ \
+# | |_) | |_| | |_| |  _  | |_| | |___ | (_| | (_) | | | | | |
+# | .__/ \__, |\____|_| |_|____/|_____(_)__,_|\___/|_| |_| |_|
+# |_|    |___/
+# =============================================================================
+# Authors:
+#   Patrick Lehmann
+#
+# Package module:   DOM: VHDL design units (e.g. context or package).
+#
+# License:
+# ============================================================================
+#  Copyright (C) 2019-2021 Tristan Gingold
+#
+#  This program is free software: you can redistribute it and/or modify
+#  it under the terms of the GNU General Public License as published by
+#  the Free Software Foundation, either version 2 of the License, or
+#  (at your option) any later version.
+#
+#  This program is distributed in the hope that it will be useful,
+#  but WITHOUT ANY WARRANTY; without even the implied warranty of
+#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+#  GNU General Public License for more details.
+#
+#  You should have received a copy of the GNU General Public License
+#  along with this program.  If not, see <gnu.org/licenses>.
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+# ============================================================================
+
+"""
+This module contains all DOM classes for VHDL's design units (:class:`context <Entity>`,
+:class:`architecture <Architecture>`, :class:`package <Package>`,
+:class:`package body <PackageBody>`, :class:`context <Context>` and
+:class:`configuration <Configuration>`.
+
+
+"""
+from pydecor import export
+
+from pyVHDLModel.PSLModel import (
+    VerificationUnit as VHDLModel_VerificationUnit,
+    VerificationProperty as VHDLModel_VerificationProperty,
+    VerificationMode as VHDLModel_VerificationMode,
+)
+
+from pyGHDL.libghdl._types import Iir
+from pyGHDL.dom import DOMMixin
+from pyGHDL.dom._Utils import GetNameOfNode
+
+
+__all__ = []
+
+
+@export
+class VerificationUnit(VHDLModel_VerificationUnit, DOMMixin):
+    def __init__(
+        self,
+        node: Iir,
+        identifier: str,
+    ):
+        super().__init__(identifier)
+        DOMMixin.__init__(self, node)
+
+    @classmethod
+    def parse(cls, vunitNode: Iir):
+        name = GetNameOfNode(vunitNode)
+
+        # FIXME: needs an implementation
+
+        return cls(vunitNode, name)
+
+
+@export
+class VerificationProperty(VHDLModel_VerificationProperty, DOMMixin):
+    def __init__(
+        self,
+        node: Iir,
+        identifier: str,
+    ):
+        super().__init__(identifier)
+        DOMMixin.__init__(self, node)
+
+    @classmethod
+    def parse(cls, vpropNode: Iir):
+        name = GetNameOfNode(vpropNode)
+
+        # FIXME: needs an implementation
+
+        return cls(vpropNode, name)
+
+
+@export
+class VerificationMode(VHDLModel_VerificationMode, DOMMixin):
+    def __init__(
+        self,
+        node: Iir,
+        identifier: str,
+    ):
+        super().__init__(identifier)
+        DOMMixin.__init__(self, node)
+
+    @classmethod
+    def parse(cls, vmodeNode: Iir):
+        name = GetNameOfNode(vmodeNode)
+
+        # FIXME: needs an implementation
+
+        return cls(vmodeNode, name)