Code cleanups.

3 files changed, 42 insertions, 88 deletions

diff --git a/pyGHDL/dom/DesignUnit.py b/pyGHDL/dom/DesignUnit.py
index ce93bda3e..7eb15aebe 100644
--- a/pyGHDL/dom/DesignUnit.py
+++ b/pyGHDL/dom/DesignUnit.py
@@ -61,54 +61,39 @@ from pyGHDL.dom._Translate import (
     GetDeclaredItemsFromChainedNodes,
 )
 from pyGHDL.dom.Symbol import EntitySymbol
-from pyGHDL.dom.Common import GHDLMixin
 
 
 __all__ = []
 
 
 @export
-class Entity(VHDLModel_Entity, GHDLMixin):
+class Entity(VHDLModel_Entity):
     @classmethod
     def parse(cls, entityNode: Iir):
         name = GetNameOfNode(entityNode)
-        entity = cls(name)
-
-        for generic in GetGenericsFromChainedNodes(nodes.Get_Generic_Chain(entityNode)):
-            entity.GenericItems.append(generic)
-
-        for port in GetPortsFromChainedNodes(nodes.Get_Port_Chain(entityNode)):
-            entity.PortItems.append(port)
-
-        for item in GetDeclaredItemsFromChainedNodes(
+        generics = GetGenericsFromChainedNodes(nodes.Get_Generic_Chain(entityNode))
+        ports = GetPortsFromChainedNodes(nodes.Get_Port_Chain(entityNode))
+        declaredItems = GetDeclaredItemsFromChainedNodes(
             nodes.Get_Declaration_Chain(entityNode), "entity", name
-        ):
-            entity.DeclaredItems.append(item)
+        )
+        bodyItems = []
 
-        return entity
+        return cls(name, generics, ports, declaredItems, bodyItems)
 
 
 @export
-class Architecture(VHDLModel_Architecture, GHDLMixin):
-    def __init__(self, name: str, entity: EntityOrSymbol):
-        super().__init__(name)
-
-        self._entity = entity
-
+class Architecture(VHDLModel_Architecture):
     @classmethod
     def parse(cls, architectureNode: Iir):
         name = GetNameOfNode(architectureNode)
         entityName = GetNameOfNode(nodes.Get_Entity_Name(architectureNode))
         entity = EntitySymbol(entityName)
-
-        architecture = cls(name, entity)
-
-        for item in GetDeclaredItemsFromChainedNodes(
+        declaredItems = GetDeclaredItemsFromChainedNodes(
             nodes.Get_Declaration_Chain(architectureNode), "architecture", name
-        ):
-            architecture.DeclaredItems.append(item)
+        )
+        bodyItems = []
 
-        return architecture
+        return cls(name, entity, declaredItems, bodyItems)
 
     def resolve(self):
         pass
@@ -119,54 +104,39 @@ class Component(VHDLModel_Component):
     @classmethod
     def parse(cls, componentNode: Iir):
         name = GetNameOfNode(componentNode)
+        generics = GetGenericsFromChainedNodes(nodes.Get_Generic_Chain(componentNode))
+        ports = GetPortsFromChainedNodes(nodes.Get_Port_Chain(componentNode))
 
-        component = cls(name)
-
-        for generic in GetGenericsFromChainedNodes(
-            nodes.Get_Generic_Chain(componentNode)
-        ):
-            component.GenericItems.append(generic)
-
-        for port in GetPortsFromChainedNodes(nodes.Get_Port_Chain(componentNode)):
-            component.PortItems.append(port)
-
-        return component
+        return cls(name, generics, ports)
 
 
 @export
-class Package(VHDLModel_Package, GHDLMixin):
+class Package(VHDLModel_Package):
     @classmethod
-    def parse(cls, libraryUnit: Iir):
-        name = GetNameOfNode(libraryUnit)
-
-        package = cls(name)
+    def parse(cls, packageNode: Iir):
+        name = GetNameOfNode(packageNode)
+        generics = None # GetGenericsFromChainedNodes(nodes.Get_Generic_Chain(packageNode))
+        declaredItems = GetDeclaredItemsFromChainedNodes(
+            nodes.Get_Declaration_Chain(packageNode), "package", name
+        )
 
-        for item in GetDeclaredItemsFromChainedNodes(
-            nodes.Get_Declaration_Chain(libraryUnit), "package", name
-        ):
-            package.DeclaredItems.append(item)
-
-        return package
+        return cls(name, generics, declaredItems)
 
 
 @export
-class PackageBody(VHDLModel_PackageBody, GHDLMixin):
+class PackageBody(VHDLModel_PackageBody):
     @classmethod
-    def parse(cls, libraryUnit: Iir):
-        name = GetNameOfNode(libraryUnit)
-
-        packageBody = cls(name)
-
-        for item in GetDeclaredItemsFromChainedNodes(
-            nodes.Get_Declaration_Chain(libraryUnit), "package body", name
-        ):
-            packageBody.DeclaredItems.append(item)
+    def parse(cls, packageBodyNode: Iir):
+        name = GetNameOfNode(packageBodyNode)
+        declaredItems = GetDeclaredItemsFromChainedNodes(
+            nodes.Get_Declaration_Chain(packageBodyNode), "package", name
+        )
 
-        return packageBody
+        return cls(name, declaredItems)
 
 
 @export
-class Context(VHDLModel_Context, GHDLMixin):
+class Context(VHDLModel_Context):
     @classmethod
     def parse(cls, libraryUnit: Iir):
         name = GetNameOfNode(libraryUnit)
@@ -174,8 +144,8 @@ class Context(VHDLModel_Context, GHDLMixin):
 
 
 @export
-class Configuration(VHDLModel_Configuration, GHDLMixin):
+class Configuration(VHDLModel_Configuration):
     @classmethod
-    def parse(cls, libraryUnit: Iir):
-        name = GetNameOfNode(libraryUnit)
+    def parse(cls, configuration: Iir):
+        name = GetNameOfNode(configuration)
         return cls(name)
diff --git a/pyGHDL/dom/InterfaceItem.py b/pyGHDL/dom/InterfaceItem.py
index eac92c8a6..e045899da 100644
--- a/pyGHDL/dom/InterfaceItem.py
+++ b/pyGHDL/dom/InterfaceItem.py
@@ -62,9 +62,7 @@ class GenericConstantInterfaceItem(VHDLModel_GenericConstantInterfaceItem):
         default = nodes.Get_Default_Value(generic)
         value = GetExpressionFromNode(default) if default else None
 
-        g = cls(name, mode, subTypeIndication, value)
-
-        return g
+        return cls(name, mode, subTypeIndication, value)
 
     def __init__(
         self,
@@ -91,9 +89,7 @@ class PortSignalInterfaceItem(VHDLModel_PortSignalInterfaceItem):
             GetExpressionFromNode(defaultValue) if defaultValue != Null_Iir else None
         )
 
-        p = cls(name, mode, subTypeIndication, value)
-
-        return p
+        return cls(name, mode, subTypeIndication, value)
 
     def __init__(
         self,
@@ -120,9 +116,7 @@ class ParameterConstantInterfaceItem(VHDLModel_ParameterConstantInterfaceItem):
             GetExpressionFromNode(defaultValue) if defaultValue != Null_Iir else None
         )
 
-        param = cls(name, mode, subTypeIndication, value)
-
-        return param
+        return cls(name, mode, subTypeIndication, value)
 
     def __init__(
         self,
@@ -149,9 +143,7 @@ class ParameterVariableInterfaceItem(VHDLModel_ParameterVariableInterfaceItem):
             GetExpressionFromNode(defaultValue) if defaultValue != Null_Iir else None
         )
 
-        param = cls(name, mode, subTypeIndication, value)
-
-        return param
+        return cls(name, mode, subTypeIndication, value)
 
     def __init__(
         self,
@@ -178,9 +170,7 @@ class ParameterSignalInterfaceItem(VHDLModel_ParameterSignalInterfaceItem):
             GetExpressionFromNode(defaultValue) if defaultValue != Null_Iir else None
         )
 
-        param = cls(name, mode, subTypeIndication, value)
-
-        return param
+        return cls(name, mode, subTypeIndication, value)
 
     def __init__(
         self,
diff --git a/pyGHDL/dom/Object.py b/pyGHDL/dom/Object.py
index 1f1f8f6d9..746971bac 100644
--- a/pyGHDL/dom/Object.py
+++ b/pyGHDL/dom/Object.py
@@ -63,9 +63,7 @@ class Constant(VHDLModel_Constant):
         subTypeIndication = GetSubtypeIndicationFromNode(node, "constant", name)
         defaultExpression = GetExpressionFromNode(nodes.Get_Default_Value(node))
 
-        constant = cls(name, subTypeIndication, defaultExpression)
-
-        return constant
+        return cls(name, subTypeIndication, defaultExpression)
 
 
 @export
@@ -85,9 +83,7 @@ class Variable(VHDLModel_Variable):
         subTypeIndication = GetSubtypeIndicationFromNode(node, "variable", name)
         defaultExpression = GetExpressionFromNode(nodes.Get_Default_Value(node))
 
-        variable = cls(name, subTypeIndication, defaultExpression)
-
-        return variable
+        return cls(name, subTypeIndication, defaultExpression)
 
 
 @export
@@ -108,6 +104,4 @@ class Signal(VHDLModel_Signal):
         default = nodes.Get_Default_Value(node)
         defaultExpression = GetExpressionFromNode(default) if default else None
 
-        signal = cls(name, subTypeIndication, defaultExpression)
-
-        return signal
+        return cls(name, subTypeIndication, defaultExpression)