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author | Patrick Lehmann <Patrick.Lehmann@plc2.de> | 2021-06-23 10:06:39 +0200 |
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committer | Patrick Lehmann <Patrick.Lehmann@plc2.de> | 2021-06-23 10:06:39 +0200 |
commit | 9fca189af9677e435a42eaae1edd91e1098596ac (patch) | |
tree | 5c93c53721534b45ba65cbe68076f612c6a4ff2b /pyGHDL/dom/Literal.py | |
parent | 1173ddab8255781e0e2bff2b92e8d07b7bf1c26d (diff) | |
download | ghdl-9fca189af9677e435a42eaae1edd91e1098596ac.tar.gz ghdl-9fca189af9677e435a42eaae1edd91e1098596ac.tar.bz2 ghdl-9fca189af9677e435a42eaae1edd91e1098596ac.zip |
Added handling of enumeration, array and record types.
Diffstat (limited to 'pyGHDL/dom/Literal.py')
-rw-r--r-- | pyGHDL/dom/Literal.py | 22 |
1 files changed, 16 insertions, 6 deletions
diff --git a/pyGHDL/dom/Literal.py b/pyGHDL/dom/Literal.py index 209712ba3..10d30b0fa 100644 --- a/pyGHDL/dom/Literal.py +++ b/pyGHDL/dom/Literal.py @@ -30,9 +30,11 @@ # # SPDX-License-Identifier: GPL-2.0-or-later # ============================================================================ +from pyGHDL.libghdl._types import Iir from pydecor import export from pyVHDLModel.VHDLModel import ( + EnumerationLiteral as VHDLModel_EnumerationLiteral, IntegerLiteral as VHDLModel_IntegerLiteral, FloatingPointLiteral as VHDLModel_FloatingPointLiteral, PhysicalIntegerLiteral as VHDLModel_PhysicalIntegerLiteral, @@ -48,9 +50,17 @@ __all__ = [] @export +class EnumerationLiteral(VHDLModel_EnumerationLiteral): + @classmethod + def parse(cls, literalNode: Iir) -> 'EnumerationLiteral': + literalName = GetNameOfNode(literalNode) + return cls(literalName) + + +@export class IntegerLiteral(VHDLModel_IntegerLiteral): @classmethod - def parse(cls, node): + def parse(cls, node: Iir) -> 'IntegerLiteral': value = nodes.Get_Value(node) return cls(value) @@ -58,7 +68,7 @@ class IntegerLiteral(VHDLModel_IntegerLiteral): @export class FloatingPointLiteral(VHDLModel_FloatingPointLiteral): @classmethod - def parse(cls, node): + def parse(cls, node: Iir) -> 'FloatingPointLiteral': value = nodes.Get_Fp_Value(node) return cls(value) @@ -66,7 +76,7 @@ class FloatingPointLiteral(VHDLModel_FloatingPointLiteral): @export class PhysicalIntegerLiteral(VHDLModel_PhysicalIntegerLiteral): @classmethod - def parse(cls, node): + def parse(cls, node: Iir) -> 'PhysicalIntegerLiteral': value = nodes.Get_Value(node) unit = nodes.Get_Unit_Name(node) unitName = GetNameOfNode(unit) @@ -77,7 +87,7 @@ class PhysicalIntegerLiteral(VHDLModel_PhysicalIntegerLiteral): @export class PhysicalFloatingLiteral(VHDLModel_PhysicalFloatingLiteral): @classmethod - def parse(cls, node): + def parse(cls, node: Iir) -> 'PhysicalFloatingLiteral': value = nodes.Get_Fp_Value(node) unit = nodes.Get_Unit_Name(node) unitName = GetNameOfNode(unit) @@ -88,7 +98,7 @@ class PhysicalFloatingLiteral(VHDLModel_PhysicalFloatingLiteral): @export class CharacterLiteral(VHDLModel_CharacterLiteral): @classmethod - def parse(cls, node): + def parse(cls, node: Iir) -> 'CharacterLiteral': identifier = nodes.Get_Identifier(node) value = name_table.Get_Character(identifier) return cls(value) @@ -97,7 +107,7 @@ class CharacterLiteral(VHDLModel_CharacterLiteral): @export class StringLiteral(VHDLModel_StringLiteral): @classmethod - def parse(cls, node): + def parse(cls, node: Iir) -> 'StringLiteral': stringID = nodes.Get_String8_Id(node) value = name_table.Get_Name_Ptr(stringID) return cls(value) |