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author | Patrick Lehmann <Patrick.Lehmann@plc2.de> | 2021-06-21 14:32:57 +0200 |
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committer | Patrick Lehmann <Patrick.Lehmann@plc2.de> | 2021-06-22 12:26:59 +0200 |
commit | e41f119ea07c83842599fdd4ff1dd8e235eb791e (patch) | |
tree | bf0605a0bc79d4862e667b0aade22c3a0002c6f0 /pyGHDL/dom/Expression.py | |
parent | ee253532230b5c1904844006e2a4bd8ec8cffc1d (diff) | |
download | ghdl-e41f119ea07c83842599fdd4ff1dd8e235eb791e.tar.gz ghdl-e41f119ea07c83842599fdd4ff1dd8e235eb791e.tar.bz2 ghdl-e41f119ea07c83842599fdd4ff1dd8e235eb791e.zip |
Handle more expressions (logical, compare, rem/mod).
Diffstat (limited to 'pyGHDL/dom/Expression.py')
-rw-r--r-- | pyGHDL/dom/Expression.py | 40 |
1 files changed, 33 insertions, 7 deletions
diff --git a/pyGHDL/dom/Expression.py b/pyGHDL/dom/Expression.py index d55ea8cef..30684394b 100644 --- a/pyGHDL/dom/Expression.py +++ b/pyGHDL/dom/Expression.py @@ -39,7 +39,7 @@ from pyVHDLModel.VHDLModel import ( IdentityExpression as VHDLModel_IdentityExpression, NegationExpression as VHDLModel_NegationExpression, AbsoluteExpression as VHDLModel_AbsoluteExpression, - ParenthesisExpression as VHDLModel_ParenthesisExpression, + SubExpression as VHDLModel_ParenthesisExpression, TypeConversion as VHDLModel_TypeConversion, FunctionCall as VHDLModel_FunctionCall, QualifiedExpression as VHDLModel_QualifiedExpression, @@ -59,9 +59,10 @@ from pyVHDLModel.VHDLModel import ( XnorExpression as VHDLModel_XnorExpression, EqualExpression as VHDLModel_EqualExpression, UnequalExpression as VHDLModel_UnequalExpression, + LessThanExpression as VHDLModel_LessThanExpression, + LessEqualExpression as VHDLModel_LessEqualExpression, GreaterThanExpression as VHDLModel_GreaterThanExpression, GreaterEqualExpression as VHDLModel_GreaterEqualExpression, - LessThanExpression as VHDLModel_LessThanExpression, ShiftRightLogicExpression as VHDLModel_ShiftRightLogicExpression, ShiftLeftLogicExpression as VHDLModel_ShiftLeftLogicExpression, ShiftRightArithmeticExpression as VHDLModel_ShiftRightArithmeticExpression, @@ -70,14 +71,14 @@ from pyVHDLModel.VHDLModel import ( RotateLeftExpression as VHDLModel_RotateLeftExpression, Aggregate as VHDLModel_Aggregate, Expression, - AggregateElement, + AggregateElement, SubTypeOrSymbol, ) from pyGHDL.libghdl import utils from pyGHDL.libghdl.vhdl import nodes from pyGHDL.dom._Utils import GetIirKindOfNode from pyGHDL.dom.Common import DOMException -from pyGHDL.dom.Symbol import EnumerationLiteralSymbol +from pyGHDL.dom.Symbol import EnumerationLiteralSymbol, SimpleSubTypeSymbol from pyGHDL.dom.Aggregates import ( OthersAggregateElement, SimpleAggregateElement, @@ -305,7 +306,7 @@ class UnequalExpression(VHDLModel_UnequalExpression, _ParseBinaryExpression): @export -class GreaterThanExpression(VHDLModel_GreaterThanExpression, _ParseBinaryExpression): +class LessThanExpression(VHDLModel_LessThanExpression, _ParseBinaryExpression): def __init__(self, left: Expression, right: Expression): super().__init__() self._leftOperand = left @@ -313,7 +314,7 @@ class GreaterThanExpression(VHDLModel_GreaterThanExpression, _ParseBinaryExpress @export -class GreaterEqualExpression(VHDLModel_GreaterEqualExpression, _ParseBinaryExpression): +class LessEqualExpression(VHDLModel_LessEqualExpression, _ParseBinaryExpression): def __init__(self, left: Expression, right: Expression): super().__init__() self._leftOperand = left @@ -321,7 +322,15 @@ class GreaterEqualExpression(VHDLModel_GreaterEqualExpression, _ParseBinaryExpre @export -class LessThanExpression(VHDLModel_LessThanExpression, _ParseBinaryExpression): +class GreaterThanExpression(VHDLModel_GreaterThanExpression, _ParseBinaryExpression): + def __init__(self, left: Expression, right: Expression): + super().__init__() + self._leftOperand = left + self._rightOperand = right + + +@export +class GreaterEqualExpression(VHDLModel_GreaterEqualExpression, _ParseBinaryExpression): def __init__(self, left: Expression, right: Expression): super().__init__() self._leftOperand = left @@ -385,6 +394,23 @@ class RotateLeftExpression(VHDLModel_RotateLeftExpression, _ParseBinaryExpressio @export +class QualifiedExpression(VHDLModel_QualifiedExpression): + def __init__(self, subType: SubTypeOrSymbol, operand: Expression): + super().__init__() + self._subtype = subType + self._operand = operand + + @classmethod + def parse(cls, node): + from pyGHDL.dom._Translate import GetExpressionFromNode, GetNameOfNode + + typeMarkName = GetNameOfNode(nodes.Get_Type_Mark(node)) + subType = SimpleSubTypeSymbol(typeMarkName) + operand = GetExpressionFromNode(nodes.Get_Expression(node)) + return cls(subType, operand) + + +@export class Aggregate(VHDLModel_Aggregate): def __init__(self, elements: List[AggregateElement]): super().__init__() |