More DOM improvements (#1806)

* First try to handle names.

* Reworked names.

* Reworked range expressions.

* Handle AttributeNames.

* Added handling of file declaration and attribute declarations.

* Improved error outputs.

* Handle protected types.

* Make black happy with ugly code.

* Handle Null literal and File parameters.

* File type and physical type.

* Don't fail on reported syntax errors.
Catch call errors into libghdl.

* Improved Sanity checks for pyGHDL.dom.

* Load sourcecode via Python and process in-memory.
Fixed testcases.

* Added package instantiations and packages with generics.

* Added UseClause, AttributeSpecification and PhysicalTypes.

* Improved pretty-printing.

* Fixed AttributeName in subtype indication.

* Get code position of IIR nodes.

* Added DOMMixin into all derived classes.

* Mark as not yet implemented.

* Pinned pyVHDLModel version to v0.10.4.

* Removed xfail in LSP test.
Bumped requirement of pyVHDLModel to v0.10.4.
Fixed some Codacy issues.

(cherry picked from commit f64e7ed7c3d69cbf84cd60db8e9b085e90b846cb)

1 files changed, 26 insertions, 12 deletions

diff --git a/pyGHDL/dom/Aggregates.py b/pyGHDL/dom/Aggregates.py
index ac8ecbca8..32dc1cacf 100644
--- a/pyGHDL/dom/Aggregates.py
+++ b/pyGHDL/dom/Aggregates.py
@@ -41,8 +41,6 @@ This module contains all DOM classes for VHDL's design units (:class:`context <E
 """
 from pydecor import export
 
-from pyGHDL.dom.Range import Range
-from pyGHDL.dom.Symbol import EnumerationLiteralSymbol
 from pyVHDLModel.VHDLModel import (
     SimpleAggregateElement as VHDLModel_SimpleAggregateElement,
     IndexedAggregateElement as VHDLModel_IndexedAggregateElement,
@@ -51,44 +49,60 @@ from pyVHDLModel.VHDLModel import (
     OthersAggregateElement as VHDLModel_OthersAggregateElement,
     Expression,
 )
+from pyGHDL.libghdl._types import Iir
+from pyGHDL.dom import DOMMixin
+from pyGHDL.dom.Range import Range
+from pyGHDL.dom.Symbol import EnumerationLiteralSymbol
 
 
 __all__ = []
 
 
 @export
-class SimpleAggregateElement(VHDLModel_SimpleAggregateElement):
-    def __init__(self, expression: Expression):
+class SimpleAggregateElement(VHDLModel_SimpleAggregateElement, DOMMixin):
+    def __init__(self, node: Iir, expression: Expression):
         super().__init__()
+        DOMMixin.__init__(self, node)
+
         self._expression = expression
 
 
 @export
-class IndexedAggregateElement(VHDLModel_IndexedAggregateElement):
-    def __init__(self, index: Expression, expression: Expression):
+class IndexedAggregateElement(VHDLModel_IndexedAggregateElement, DOMMixin):
+    def __init__(self, node: Iir, index: Expression, expression: Expression):
         super().__init__()
+        DOMMixin.__init__(self, node)
+
         self._index = index
         self._expression = expression
 
 
 @export
-class RangedAggregateElement(VHDLModel_RangedAggregateElement):
-    def __init__(self, r: Range, expression: Expression):
+class RangedAggregateElement(VHDLModel_RangedAggregateElement, DOMMixin):
+    def __init__(self, node: Iir, r: Range, expression: Expression):
         super().__init__()
+        DOMMixin.__init__(self, node)
+
         self._range = r
         self._expression = expression
 
 
 @export
-class NamedAggregateElement(VHDLModel_NamedAggregateElement):
-    def __init__(self, name: EnumerationLiteralSymbol, expression: Expression):
+class NamedAggregateElement(VHDLModel_NamedAggregateElement, DOMMixin):
+    def __init__(
+        self, node: Iir, name: EnumerationLiteralSymbol, expression: Expression
+    ):
         super().__init__()
+        DOMMixin.__init__(self, node)
+
         self._name = name
         self._expression = expression
 
 
 @export
-class OthersAggregateElement(VHDLModel_OthersAggregateElement):
-    def __init__(self, expression: Expression):
+class OthersAggregateElement(VHDLModel_OthersAggregateElement, DOMMixin):
+    def __init__(self, node: Iir, expression: Expression):
         super().__init__()
+        DOMMixin.__init__(self, node)
+
         self._expression = expression