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| author | Tristan Gingold <tgingold@free.fr> | 2014-11-06 07:00:38 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2014-11-06 07:00:38 +0100 |
| commit | 30e6f0ac82456a8d5e39e88b113bef635fc6877e (patch) | |
| tree | f81c544f65a76c62ce98e62b9eca50d582e2c493 /libraries/Makefile.inc | |
| parent | 338c27598d9ca5de600b51d942de498dee5d6306 (diff) | |
| download | ghdl-30e6f0ac82456a8d5e39e88b113bef635fc6877e.tar.gz ghdl-30e6f0ac82456a8d5e39e88b113bef635fc6877e.tar.bz2 ghdl-30e6f0ac82456a8d5e39e88b113bef635fc6877e.zip | |
mcode build and install from top makefile.
Diffstat (limited to 'libraries/Makefile.inc')
| -rw-r--r-- | libraries/Makefile.inc | 15 |
1 files changed, 12 insertions, 3 deletions
diff --git a/libraries/Makefile.inc b/libraries/Makefile.inc index 8979f243b..67a2dff59 100644 --- a/libraries/Makefile.inc +++ b/libraries/Makefile.inc @@ -140,7 +140,10 @@ synopsys.v93: $(LIB93_DIR) $(SYNOPSYS_SRCS) force $(CP) ../ieee/ieee-obj93.cf .; \ test x$(VHDLLIBS_COPY_OBJS) = "xno" || \ for i in $(IEEE_SRCS) $(MATH_SRCS) $(VITAL2000_SRCS); do \ - b=`basename $$i .vhdl`; $(LN) ../ieee/$$b.o $$b.o || exit 1; \ + b=`basename $$i .vhdl`; \ + if [ -f ../ieee/$$b.o ]; then \ + $(LN) ../ieee/$$b.o $$b.o || exit 1; \ + fi; \ done; \ for i in $(SYNOPSYS93_BSRCS); do \ cmd="$(ANALYZE_IEEE93) $(REL_DIR)/$(LIBSRC_DIR)/$$i"; \ @@ -155,7 +158,10 @@ mentor.v93: $(LIB93_DIR) $(MENTOR93_SRCS) force $(CP) ../ieee/ieee-obj93.cf . ;\ test x$(VHDLLIBS_COPY_OBJS) = "xno" || \ for i in $(IEEE_SRCS) $(MATH_SRCS) $(VITAL2000_SRCS); do \ - b=`basename $$i .vhdl`; $(LN) ../ieee/$$b.o $$b.o || exit 1; \ + b=`basename $$i .vhdl`; \ + if [ -f ../ieee/$$b.o ]; then \ + $(LN) ../ieee/$$b.o $$b.o || exit 1; \ + fi; \ done ; \ for i in $(MENTOR93_BSRCS); do \ cmd="$(ANALYZE_IEEE93) $(REL_DIR)/$(LIBSRC_DIR)/$$i";\ @@ -191,7 +197,10 @@ synopsys.v87: $(LIB87_DIR) $(SYNOPSYS_SRCS) force $(CP) ../ieee/ieee-obj87.cf . ; \ test x$(VHDLLIBS_COPY_OBJS) = "xno" || \ for i in $(IEEE_SRCS) $(VITAL95_SRCS); do \ - b=`basename $$i .vhdl`; $(LN) ../ieee/$$b.o $$b.o || exit 1; \ + b=`basename $$i .vhdl`; \ + if [ -f ../ieee/$$b.o ]; then \ + $(LN) ../ieee/$$b.o $$b.o || exit 1; \ + fi; \ done; \ for i in $(SYNOPSYS87_BSRCS); do \ cmd="$(ANALYZE_IEEE87) $(REL_DIR)/$(LIBSRC_DIR)/$$i";\ |