Standardize indentation to 2 spaces

Change indentation within documentation code blocks to 2 space indents
instead of 3.

4 files changed, 201 insertions, 201 deletions

diff --git a/doc/references/CodingStyle.rst b/doc/references/CodingStyle.rst
index 2fb09c6ef..b9da53804 100644
--- a/doc/references/CodingStyle.rst
+++ b/doc/references/CodingStyle.rst
@@ -10,7 +10,7 @@ Use assertions.
 
 We try to follow the 'GNU Coding Standards' when possible: comments before
 declarations, two spaces at end of sentences, finish sentences with a dot.
-But: 3 spaces for indentation.
+But: 2 spaces for indentation in code blocks.
 
 No trailing spaces, no TAB (HT).
 
@@ -82,7 +82,7 @@ declaration).  Don't repeat the comment before the subprogram body.
   
         procedure Translate_Assign (Target : Mnode; Expr : Iir; Target_Type : Iir)
         is
-           Val : O_Enode;
+          Val : O_Enode;
         begin
 				
   vs.
@@ -130,9 +130,9 @@ declaration).  Don't repeat the comment before the subprogram body.
      .. code-block:: Ada
   
         is
-           N_Info : constant Iir := Get_Sub_Aggregate_Info (Info);
-           Assoc  : Iir;
-           Sub    : Iir;
+          N_Info : constant Iir := Get_Sub_Aggregate_Info (Info);
+          Assoc  : Iir;
+          Sub    : Iir;
         begin
 				
   If the initialization expression has a side effect (such as allocation), do
diff --git a/doc/references/ImplementationOfVHDL.rst b/doc/references/ImplementationOfVHDL.rst
index 0074d2c7c..0169d7ad8 100644
--- a/doc/references/ImplementationOfVHDL.rst
+++ b/doc/references/ImplementationOfVHDL.rst
@@ -355,7 +355,7 @@ in Ada:
   with System;
   ...
   function Ghdl_Main (Argc : Integer; Argv : System.Address)
-     return Integer;
+    return Integer;
   pragma import (C, Ghdl_Main, "ghdl_main");
 
 
@@ -445,26 +445,26 @@ level design name.
   with Ghdl_Main;
 
   procedure Test_Grt is
-     --  VHPI handle.
-     H : VhpiHandleT;
-     Status : Integer;
+    --  VHPI handle.
+    H : VhpiHandleT;
+    Status : Integer;
 
-     --  Name.
-     Name : String (1 .. 64);
-     Name_Len : Integer;
+    --  Name.
+    Name : String (1 .. 64);
+    Name_Len : Integer;
   begin
-     --  Elaborate and run the design.
-     Status := Ghdl_Main (0, Null_Address);
+    --  Elaborate and run the design.
+    Status := Ghdl_Main (0, Null_Address);
 
-     --  Display the status of the simulation.
-     Put_Line ("Status is " & Integer'Image (Status));
+    --  Display the status of the simulation.
+    Put_Line ("Status is " & Integer'Image (Status));
 
-     --  Get the root instance.
-     Get_Root_Inst(H);
+    --  Get the root instance.
+    Get_Root_Inst(H);
 
-     --  Disp its name using vhpi API.
-     Vhpi_Get_Str (VhpiNameP, H, Name, Name_Len);
-     Put_Line ("Root instance name: " & Name (1 .. Name_Len));
+    --  Disp its name using vhpi API.
+    Vhpi_Get_Str (VhpiNameP, H, Name, Name_Len);
+    Put_Line ("Root instance name: " & Name (1 .. Name_Len));
   end Test_Grt;
 
 
diff --git a/doc/using/InvokingGHDL.rst b/doc/using/InvokingGHDL.rst
index 931b1115e..f857563c5 100644
--- a/doc/using/InvokingGHDL.rst
+++ b/doc/using/InvokingGHDL.rst
@@ -300,12 +300,12 @@ Options
   .. code-block:: VHDL
 
    package pkg1 is
-      type state is (state1, state2, state3);
+     type state is (state1, state2, state3);
    end pkg1;
 
    use work.pkg1.all;
    package pkg2 is
-      constant state1 : state := state1;
+     constant state1 : state := state1;
    end pkg2;
 
   Some code (such as Xilinx packages) have such constructs, which are valid.
@@ -580,38 +580,38 @@ When you use options :option:`--ieee=synopsys` or :option:`--ieee=mentor`, the `
 
 .. code-block:: VHDL
 
-   library ieee;
-   use ieee.std_logic_1164.all;
-
-   --  A counter from 0 to 10.
-   entity counter is
-      port (val : out std_logic_vector (3 downto 0);
-            ck : std_logic;
-            rst : std_logic);
-   end counter;
-
-   library ieee;
-   use ieee.std_logic_unsigned.all;
-
-   architecture bad of counter
-   is
-      signal v : std_logic_vector (3 downto 0);
-   begin
-      process (ck, rst)
-      begin
-        if rst = '1' then
-           v <= x"0";
-        elsif rising_edge (ck) then
-           if v = "1010" then -- Error
-              v <= x"0";
-           else
-              v <= v + 1;
-           end if;
+  library ieee;
+  use ieee.std_logic_1164.all;
+
+  --  A counter from 0 to 10.
+  entity counter is
+    port (val : out std_logic_vector (3 downto 0);
+          ck : std_logic;
+          rst : std_logic);
+  end counter;
+
+  library ieee;
+  use ieee.std_logic_unsigned.all;
+
+  architecture bad of counter
+  is
+    signal v : std_logic_vector (3 downto 0);
+  begin
+    process (ck, rst)
+    begin
+      if rst = '1' then
+        v <= x"0";
+      elsif rising_edge (ck) then
+        if v = "1010" then -- Error
+          v <= x"0";
+        else
+          v <= v + 1;
         end if;
-      end process;
+      end if;
+    end process;
 
-      val <= v;
-   end bad;
+    val <= v;
+  end bad;
 
 
 When you analyze this design, GHDL does not accept it (two long lines have been split for readability):
@@ -636,55 +636,55 @@ You can force GHDL to use this rule with the *-fexplicit* option (see ':ref:`GHD
 
 .. code-block:: VHDL
 
-   library ieee;
-   use ieee.std_logic_unsigned.all;
-
-   architecture fixed_bad of counter
-   is
-      signal v : std_logic_vector (3 downto 0);
-   begin
-      process (ck, rst)
-      begin
-         if rst = '1' then
-            v <= x"0";
-         elsif rising_edge (ck) then
-            if ieee.std_logic_unsigned."=" (v, "1010") then
-               v <= x"0";
-            else
-               v <= v + 1;
-            end if;
-         end if;
-      end process;
-
-      val <= v;
-   end fixed_bad;
+  library ieee;
+  use ieee.std_logic_unsigned.all;
+
+  architecture fixed_bad of counter
+  is
+    signal v : std_logic_vector (3 downto 0);
+  begin
+    process (ck, rst)
+    begin
+      if rst = '1' then
+        v <= x"0";
+      elsif rising_edge (ck) then
+        if ieee.std_logic_unsigned."=" (v, "1010") then
+          v <= x"0";
+        else
+          v <= v + 1;
+        end if;
+      end if;
+    end process;
+
+    val <= v;
+  end fixed_bad;
 
 It is better to only use the standard packages defined by IEEE, which provide the same functionalities:
 
 .. code-block:: VHDL
 
-   library ieee;
-   use ieee.numeric_std.all;
-
-   architecture good of counter
-   is
-      signal v : unsigned (3 downto 0);
-   begin
-      process (ck, rst)
-      begin
-         if rst = '1' then
-            v <= x"0";
-         elsif rising_edge (ck) then
-            if v = "1010" then
-               v <= x"0";
-            else
-               v <= v + 1;
-            end if;
-         end if;
-      end process;
-
-      val <= std_logic_vector (v);
-   end good;
+  library ieee;
+  use ieee.numeric_std.all;
+
+  architecture good of counter
+  is
+    signal v : unsigned (3 downto 0);
+  begin
+    process (ck, rst)
+    begin
+      if rst = '1' then
+        v <= x"0";
+      elsif rising_edge (ck) then
+        if v = "1010" then
+          v <= x"0";
+        else
+          v <= v + 1;
+        end if;
+      end if;
+    end process;
+
+    val <= std_logic_vector (v);
+  end good;
 
 .. index:: Math_Real
 
diff --git a/doc/using/QuickStartGuide.rst b/doc/using/QuickStartGuide.rst
index 803fd95f0..c332e58c3 100644
--- a/doc/using/QuickStartGuide.rst
+++ b/doc/using/QuickStartGuide.rst
@@ -13,23 +13,23 @@ To illustrate the general purpose of `VHDL`, here is a commented `'Hello world'`
 
 .. code-block:: VHDL
 
-   --  Hello world program
-   use std.textio.all; -- Imports the standard textio package.
-
-   --  Defines a design entity, without any ports.
-   entity hello_world is
-   end hello_world;
-
-   architecture behaviour of hello_world is
-   begin
-      process
-         variable l : line;
-      begin
-         write (l, String'("Hello world!"));
-         writeline (output, l);
-         wait;
-      end process;
-   end behaviour;
+  --  Hello world program
+  use std.textio.all; -- Imports the standard textio package.
+
+  --  Defines a design entity, without any ports.
+  entity hello_world is
+  end hello_world;
+
+  architecture behaviour of hello_world is
+  begin
+    process
+      variable l : line;
+    begin
+      write (l, String'("Hello world!"));
+      writeline (output, l);
+      wait;
+    end process;
+  end behaviour;
 
 .. TIP::
 
@@ -42,7 +42,7 @@ To illustrate the general purpose of `VHDL`, here is a commented `'Hello world'`
 
 .. code-block:: shell
 
-   Hello world!
+  Hello world!
 
 .. HINT::
    If a GCC/LLVM variant of `GHDL` is used:
@@ -58,21 +58,21 @@ The `heartbeat` program
 
 .. code-block:: VHDL
 
-   entity hello_world is
-      port ( clk: out std_logic; )
-   end hearbeat;
-
-   architecture behaviour of hello_world is
-   begin
-      -- Clock process definition
-      clk_process: process
-      begin
-         clk <= '0';
-         wait for clk_period/2;
-         clk <= '1';
-         wait for clk_period/2;
-      end process;
-   end behaviour;
+  entity hello_world is
+    port ( clk: out std_logic; )
+  end hearbeat;
+
+  architecture behaviour of hello_world is
+  begin
+    -- Clock process definition
+    clk_process: process
+    begin
+      clk <= '0';
+      wait for clk_period/2;
+      clk <= '1';
+      wait for clk_period/2;
+    end process;
+  end behaviour;
 
 A full adder
 ============
@@ -81,82 +81,82 @@ VHDL is generally used for hardware design. This example starts with a `full add
 
 .. code-block:: VHDL
 
-   entity adder is
-      -- `i0`, `i1`, and the carry-in `ci` are inputs of the adder.
-      -- `s` is the sum output, `co` is the carry-out.
-      port (i0, i1 : in bit; ci : in bit; s : out bit; co : out bit);
-   end adder;
-
-   architecture rtl of adder is
-   begin
-      --  This full-adder architecture contains two concurrent assignments.
-      --  Compute the sum.
-      s <= i0 xor i1 xor ci;
-      --  Compute the carry.
-      co <= (i0 and i1) or (i0 and ci) or (i1 and ci);
-   end rtl;
+  entity adder is
+    -- `i0`, `i1`, and the carry-in `ci` are inputs of the adder.
+    -- `s` is the sum output, `co` is the carry-out.
+    port (i0, i1 : in bit; ci : in bit; s : out bit; co : out bit);
+  end adder;
+
+  architecture rtl of adder is
+  begin
+    --  This full-adder architecture contains two concurrent assignments.
+    --  Compute the sum.
+    s <= i0 xor i1 xor ci;
+    --  Compute the carry.
+    co <= (i0 and i1) or (i0 and ci) or (i1 and ci);
+  end rtl;
 
 You can analyze this design file, ``ghdl -a adder.vhdl``, and try to execute the `adder` design. But this is useless, since nothing externally visible will happen. In order to check this full adder, a :dfn:`testbench` has to be run. This testbench is very simple, since the adder is also simple: it checks exhaustively all inputs.  Note that only the behaviour is tested, timing constraints are not checked. A file named :file:`adder_tb.vhdl` contains the testbench for the adder:
 
 .. code-block:: VHDL
 
-   --  A testbench has no ports.
-   entity adder_tb is
-   end adder_tb;
-
-   architecture behav of adder_tb is
-      --  Declaration of the component that will be instantiated.
-      component adder
-         port (i0, i1 : in bit; ci : in bit; s : out bit; co : out bit);
-      end component;
-
-      --  Specifies which entity is bound with the component.
-      for adder_0: adder use entity work.adder;
-      signal i0, i1, ci, s, co : bit;
-   begin
-      --  Component instantiation.
-      adder_0: adder port map (i0 => i0, i1 => i1, ci => ci,
-                               s => s, co => co);
-
-      --  This process does the real job.
-      process
-         type pattern_type is record
-            --  The inputs of the adder.
-            i0, i1, ci : bit;
-            --  The expected outputs of the adder.
-            s, co : bit;
-         end record;
-         --  The patterns to apply.
-         type pattern_array is array (natural range <>) of pattern_type;
-         constant patterns : pattern_array :=
-            (('0', '0', '0', '0', '0'),
-             ('0', '0', '1', '1', '0'),
-             ('0', '1', '0', '1', '0'),
-             ('0', '1', '1', '0', '1'),
-             ('1', '0', '0', '1', '0'),
-             ('1', '0', '1', '0', '1'),
-             ('1', '1', '0', '0', '1'),
-             ('1', '1', '1', '1', '1'));
-      begin
-         --  Check each pattern.
-         for i in patterns'range loop
-            --  Set the inputs.
-            i0 <= patterns(i).i0;
-            i1 <= patterns(i).i1;
-            ci <= patterns(i).ci;
-            --  Wait for the results.
-            wait for 1 ns;
-            --  Check the outputs.
-            assert s = patterns(i).s
-               report "bad sum value" severity error;
-            assert co = patterns(i).co
-               report "bad carry out value" severity error;
-         end loop;
-         assert false report "end of test" severity note;
-         --  Wait forever; this will finish the simulation.
-         wait;
-      end process;
-   end behav;
+  --  A testbench has no ports.
+  entity adder_tb is
+  end adder_tb;
+
+  architecture behav of adder_tb is
+    --  Declaration of the component that will be instantiated.
+    component adder
+      port (i0, i1 : in bit; ci : in bit; s : out bit; co : out bit);
+    end component;
+
+    --  Specifies which entity is bound with the component.
+    for adder_0: adder use entity work.adder;
+    signal i0, i1, ci, s, co : bit;
+  begin
+    --  Component instantiation.
+    adder_0: adder port map (i0 => i0, i1 => i1, ci => ci,
+                             s => s, co => co);
+
+    --  This process does the real job.
+    process
+      type pattern_type is record
+        --  The inputs of the adder.
+        i0, i1, ci : bit;
+        --  The expected outputs of the adder.
+        s, co : bit;
+      end record;
+      --  The patterns to apply.
+      type pattern_array is array (natural range <>) of pattern_type;
+      constant patterns : pattern_array :=
+        (('0', '0', '0', '0', '0'),
+         ('0', '0', '1', '1', '0'),
+         ('0', '1', '0', '1', '0'),
+         ('0', '1', '1', '0', '1'),
+         ('1', '0', '0', '1', '0'),
+         ('1', '0', '1', '0', '1'),
+         ('1', '1', '0', '0', '1'),
+         ('1', '1', '1', '1', '1'));
+    begin
+      --  Check each pattern.
+      for i in patterns'range loop
+        --  Set the inputs.
+        i0 <= patterns(i).i0;
+        i1 <= patterns(i).i1;
+        ci <= patterns(i).ci;
+        --  Wait for the results.
+        wait for 1 ns;
+        --  Check the outputs.
+        assert s = patterns(i).s
+          report "bad sum value" severity error;
+        assert co = patterns(i).co
+          report "bad carry out value" severity error;
+      end loop;
+      assert false report "end of test" severity note;
+      --  Wait forever; this will finish the simulation.
+      wait;
+    end process;
+  end behav;
 
 
 As usual, you should analyze the design, ``ghdl -a adder_tb.vhdl``.