Reduce after-sentence spacing to one space

During PR 591 it was decided that all sentences should be ended with
a period and then followed by only one space. Regex changed 132
instances of two spaces to one space (in 7 files).

Also changed the second paragraph of CodingStyle to dictate the use
of one space instead of two.

7 files changed, 125 insertions, 125 deletions

diff --git a/doc/references/CodingStyle.rst b/doc/references/CodingStyle.rst
index b9da53804..6af869067 100644
--- a/doc/references/CodingStyle.rst
+++ b/doc/references/CodingStyle.rst
@@ -4,12 +4,12 @@ Coding Style
 ############
 
 Ada subset: use only a simple (VHDL like) subset of Ada: no tasking, no
-controlled types...  VHDL users should easily understand that subset.
+controlled types... VHDL users should easily understand that subset.
 Allowed Ada95 features: the standard library, child packages.
 Use assertions.
 
 We try to follow the 'GNU Coding Standards' when possible: comments before
-declarations, two spaces at end of sentences, finish sentences with a dot.
+declarations, one space at the end of sentences, finish sentences with a dot.
 But: 2 spaces for indentation in code blocks.
 
 No trailing spaces, no TAB (HT).
@@ -22,7 +22,7 @@ Subprograms must have a comment before to describe them, like:
    procedure Sem_Concurrent_Statement_Chain (Parent : Iir);
 
 The line before the comment must be a blank line (unless this is the first
-declaration).  Don't repeat the comment before the subprogram body.
+declaration). Don't repeat the comment before the subprogram body.
 
 * For subprograms:
 
diff --git a/doc/references/CommandReference.rst b/doc/references/CommandReference.rst
index 06fdb7396..de6ff5415 100644
--- a/doc/references/CommandReference.rst
+++ b/doc/references/CommandReference.rst
@@ -24,7 +24,7 @@ Help [``-h``]
 .. option:: --help, -h
 
 Display (on the standard output) a short description of the all the commands
-available.  If the help switch is followed by a command switch, then options
+available. If the help switch is followed by a command switch, then options
 for that second command are displayed::
 
   ghdl --help
@@ -126,7 +126,7 @@ Bind [``--bind``]
 
 .. option:: --bind <[options] primary_unit [secondary_unit]>
 
-Performs only the first stage of the elaboration command; the list of object files is created but the executable is not built.  This command should be used only when the main entry point is not GHDL.
+Performs only the first stage of the elaboration command; the list of object files is created but the executable is not built. This command should be used only when the main entry point is not GHDL.
 
 .. index:: cmd GCC/LLVM linking
 
@@ -155,25 +155,25 @@ Allow multi-bytes chars in a comment.
 
 .. option:: --syn-binding
 
-Use synthesizer rules for component binding.  During elaboration, if a component is not bound to an entity using VHDL LRM rules, try to find in any known library an entity whose name is the same as the component name.
+Use synthesizer rules for component binding. During elaboration, if a component is not bound to an entity using VHDL LRM rules, try to find in any known library an entity whose name is the same as the component name.
 
 This rule is known as the synthesizer rule.
 
-There are two key points: normal VHDL LRM rules are tried first and entities are searched only in known libraries.  A known library is a library which has been named in your design.
+There are two key points: normal VHDL LRM rules are tried first and entities are searched only in known libraries. A known library is a library which has been named in your design.
 
 This option is only useful during elaboration.
 
 .. option:: --GHDL1<=COMMAND>
 
-Use ``COMMAND`` as the command name for the compiler.  If ``COMMAND`` is not a path, then it is searched in the path.
+Use ``COMMAND`` as the command name for the compiler. If ``COMMAND`` is not a path, then it is searched in the path.
 
 .. option:: --AS<=COMMAND>
 
-Use ``COMMAND`` as the command name for the assembler.  If ``COMMAND`` is not a path, then it is searched in the path.  The default is ``as``.
+Use ``COMMAND`` as the command name for the assembler. If ``COMMAND`` is not a path, then it is searched in the path. The default is ``as``.
 
 .. option:: --LINK<=COMMAND>
 
-Use ``COMMAND`` as the linker driver.  If ``COMMAND`` is not a path, then it is searched in the path.  The default is ``gcc``.
+Use ``COMMAND`` as the linker driver. If ``COMMAND`` is not a path, then it is searched in the path. The default is ``gcc``.
 
 Passing options to other programs
 =================================
diff --git a/doc/references/ImplementationOfVHDL.rst b/doc/references/ImplementationOfVHDL.rst
index 3cb766e2c..90cedc825 100644
--- a/doc/references/ImplementationOfVHDL.rst
+++ b/doc/references/ImplementationOfVHDL.rst
@@ -43,11 +43,11 @@ since most of the VHDL tools are still based on this standard.
 Various problems of this first standard have been analyzed by experts groups
 to give reasonable ways of interpreting the unclear portions of the standard.
 
-VHDL was revised in 1993 by IEEE as IEEE 1076-1993.  This revision is still
+VHDL was revised in 1993 by IEEE as IEEE 1076-1993. This revision is still
 well-known.
 
 Unfortunately, VHDL-93 is not fully compatible with VHDL-87, i.e. some perfectly
-valid VHDL-87 programs are invalid VHDL-93 programs.  Here are some of the
+valid VHDL-87 programs are invalid VHDL-93 programs. Here are some of the
 reasons:
 
 * the syntax of file declaration has changed (this is the most visible source
@@ -59,16 +59,16 @@ reasons:
 * rules have been added.
 
 Shared variables were replaced by protected types in the 2000 revision of
-the VHDL standard.  This modification is also known as 1076a.  Note that this
+the VHDL standard. This modification is also known as 1076a. Note that this
 standard is not fully backward compatible with VHDL-93, since the type of a
 shared variable must now be a protected type (there was no such restriction
 before).
 
-Minor corrections were added by the 2002 revision of the VHDL standard.  This
+Minor corrections were added by the 2002 revision of the VHDL standard. This
 revision is not fully backward compatible with VHDL-00 since, for example,
 the value of the `'instance_name` attribute has slightly changed.
 
-The latest version is 2008.  Many features have been added, and GHDL
+The latest version is 2008. Many features have been added, and GHDL
 doesn't implement all of them.
 
 You can select the VHDL standard expected by GHDL with the
@@ -77,7 +77,7 @@ table below:
 
 
 87
-  Select VHDL-87 standard as defined by IEEE 1076-1987.  LRM bugs corrected by
+  Select VHDL-87 standard as defined by IEEE 1076-1987. LRM bugs corrected by
   later revisions are taken into account.
 
 93
@@ -89,7 +89,7 @@ table below:
 
   * VHDL-87 file declarations are accepted;
 
-  * default binding indication rules of VHDL-02 are used.  Default binding rules
+  * default binding indication rules of VHDL-02 are used. Default binding rules
     are often used, but they are particularly obscure before VHDL-02.
 
 00
@@ -102,7 +102,7 @@ table below:
   Select VHDL-2008 standard (partially implemented).
 
 The 93, 93c, 00 and 02 standards are considered compatible: you can
-elaborate a design mixing these standards.  However, 87, 93 and 08 are
+elaborate a design mixing these standards. However, 87, 93 and 08 are
 not compatible.
 
 .. _psl_implementation:
@@ -117,7 +117,7 @@ As PSL annotations are embedded within comments, you must analyze and elaborate
 your design with option *-fpsl* to enable PSL annotations.
 
 A PSL assertion statement must appear within a comment that starts
-with the `psl` keyword.  The keyword must be followed (on the
+with the `psl` keyword. The keyword must be followed (on the
 same line) by a PSL keyword such as `assert` or `default`.
 To continue a PSL statement on the next line, just start a new comment.
 
@@ -155,7 +155,7 @@ independently analyzed.
 
 Several design units may be grouped into a design file.
 
-In GHDL, a system file represents a design file.  That is, a file compiled by
+In GHDL, a system file represents a design file. That is, a file compiled by
 GHDL may contain one or more design units.
 
 It is common to have several design units in a design file.
@@ -165,9 +165,9 @@ GHDL does not impose any restriction on the name of a design file
 spaces).
 
 GHDL does not keep a binary representation of the design units analyzed like
-other VHDL analyzers.  The sources of the design units are re-read when
+other VHDL analyzers. The sources of the design units are re-read when
 needed (for example, an entity is re-read when one of its architectures is
-analyzed).  Therefore, if you delete or modify a source file of a unit
+analyzed). Therefore, if you delete or modify a source file of a unit
 analyzed, GHDL will refuse to use it.
 
 .. _Library_database:
@@ -175,17 +175,17 @@ analyzed, GHDL will refuse to use it.
 Library database
 ================
 
-Each design unit analyzed is placed into a design library.  By default,
+Each design unit analyzed is placed into a design library. By default,
 the name of this design library is ``work``; however, this can be
 changed with the :option:`--work=NAME` option of GHDL.
 
 To keep the list of design units in a design library, GHDL creates
-library files.  The name of these files is :file:`NAME-objVER.cf`, where
+library files. The name of these files is :file:`NAME-objVER.cf`, where
 `NAME` is the name of the library, and `VER` the VHDL version (87,
 93 or 08) used to analyze the design units.
 
-You don't have to know how to read a library file.  You can display it
-using the *-d* of `ghdl`.  The file contains the name of the
+You don't have to know how to read a library file. You can display it
+using the *-d* of `ghdl`. The file contains the name of the
 design units, as well as the location and the dependencies.
 
 The format may change with the next version of GHDL.
@@ -205,12 +205,12 @@ hierarchy:
 Using vendor libraries
 ======================
 
-Many vendors libraries have been analyzed with GHDL.  There are
-usually no problems.  Be sure to use the :option:`--work=` option.
+Many vendors libraries have been analyzed with GHDL. There are
+usually no problems. Be sure to use the :option:`--work=` option.
 However, some problems have been encountered.
 
 GHDL follows the VHDL LRM (the manual which defines VHDL) more
-strictly than other VHDL tools.  You could try to relax the
+strictly than other VHDL tools. You could try to relax the
 restrictions by using the :option:`--std=93c`, :option:`-fexplicit`,
 :option:`-frelaxed-rules` and :option:`--warn-no-vital-generic`.
 
@@ -236,7 +236,7 @@ Foreign declarations
 --------------------
 
 Only subprograms (functions or procedures) can be imported, using the foreign
-attribute.  In this example, the `sin` function is imported:
+attribute. In this example, the `sin` function is imported:
 
 .. code-block:: VHDL
 
@@ -254,20 +254,20 @@ attribute.  In this example, the `sin` function is imported:
 
 
 A subprogram is made foreign if the `foreign` attribute decorates
-it.  This attribute is declared in the 1993 revision of the
-``std.standard`` package.  Therefore, you cannot use this feature in
+it. This attribute is declared in the 1993 revision of the
+``std.standard`` package. Therefore, you cannot use this feature in
 VHDL 1987.
 
-The decoration is achieved through an attribute specification.  The
+The decoration is achieved through an attribute specification. The
 attribute specification must be in the same declarative part as the
-subprogram and must be after it.  This is a general rule for specifications.
+subprogram and must be after it. This is a general rule for specifications.
 The value of the specification must be a locally static string.
 
-Even when a subprogram is foreign, its body must be present.  However, since
+Even when a subprogram is foreign, its body must be present. However, since
 it won't be called, you can make it empty or simply put an assertion.
 
 The value of the attribute must start with ``VHPIDIRECT`` (an
-upper-case keyword followed by one or more blanks).  The linkage name of the
+upper-case keyword followed by one or more blanks). The linkage name of the
 subprogram follows.
 
 .. _Restrictions_on_foreign_declarations:
@@ -275,33 +275,33 @@ subprogram follows.
 Restrictions on foreign declarations
 ------------------------------------
 
-Any subprogram can be imported.  GHDL puts no restrictions on foreign
-subprograms.  However, the representation of a type or of an interface in a
-foreign language may be obscure.  Most non-composite types are easily imported:
+Any subprogram can be imported. GHDL puts no restrictions on foreign
+subprograms. However, the representation of a type or of an interface in a
+foreign language may be obscure. Most non-composite types are easily imported:
 
 
 *integer types*
-  They are represented by a 32 bit word.  This generally corresponds to
+  They are represented by a 32 bit word. This generally corresponds to
   `int` for `C` or `Integer` for `Ada`.
 
 *physical types*
-  They are represented by a 64 bit word.  This generally corresponds to the
+  They are represented by a 64 bit word. This generally corresponds to the
   `long long` for `C` or `Long_Long_Integer` for `Ada`.
 
 *floating point types*
-  They are represented by a 64 bit floating point word.  This generally
+  They are represented by a 64 bit floating point word. This generally
   corresponds to `double` for `C` or `Long_Float` for `Ada`.
 
 *enumeration types*
   They are represented by an 8 bit word, or, if the number of literals is
-  greater than 256, by a 32 bit word.  There is no corresponding C type, since arguments are
+  greater than 256, by a 32 bit word. There is no corresponding C type, since arguments are
   not promoted.
 
-Non-composite types are passed by value.  For the `in` mode, this
-corresponds to the `C` or `Ada` mechanism.  The `out` and
+Non-composite types are passed by value. For the `in` mode, this
+corresponds to the `C` or `Ada` mechanism. The `out` and
 `inout` interfaces of non-composite types are gathered in a record
 and this record is passed by reference as the first argument to the
-subprogram.  As a consequence, you shouldn't use `in` and
+subprogram. As a consequence, you shouldn't use `in` and
 `inout` modes in foreign subprograms, since they are not portable.
 
 Records are represented like a `C` structure and are passed by reference
@@ -310,10 +310,10 @@ to subprograms.
 Arrays with static bounds are represented like a `C` array, whose
 length is the number of elements, and are passed by reference to subprograms.
 
-Unconstrained arrays are represented by a fat pointer.  Do not use unconstrained
+Unconstrained arrays are represented by a fat pointer. Do not use unconstrained
 arrays in foreign subprograms.
 
-Accesses to an unconstrained array are fat pointers.  Other accesses correspond to an address and are passed to a subprogram like other non-composite types.
+Accesses to an unconstrained array are fat pointers. Other accesses correspond to an address and are passed to a subprogram like other non-composite types.
 
 Files are represented by a 32 bit word, which corresponds to an index
 in a table.
@@ -339,7 +339,7 @@ Note the :file:`c` library is always linked with an executable.
 Starting a simulation from a foreign program
 --------------------------------------------
 
-You may run your design from an external program.  You just have to call
+You may run your design from an external program. You just have to call
 the ``ghdl_main`` function which can be defined:
 
 in C:
@@ -360,7 +360,7 @@ in Ada:
 
 
 This function must be called once, and returns 0 at the end of the simulation.
-In case of failure, this function does not return.  This has to be fixed.
+In case of failure, this function does not return. This has to be fixed.
 
 .. _Linking_with_Ada:
 
@@ -368,18 +368,18 @@ Linking with Ada
 ----------------
 
 As explained previously in :ref:`Starting_a_simulation_from_a_foreign_program`,
-you can start a simulation from an `Ada` program.  However the build
+you can start a simulation from an `Ada` program. However the build
 process is not trivial: you have to elaborate your `Ada` program and your
 `VHDL` design.
 
-First, you have to analyze all your design files.  In this example, we
+First, you have to analyze all your design files. In this example, we
 suppose there is only one design file, :file:`design.vhdl`.
 
 ::
 
   $ ghdl -a design.vhdl
 
-Then, bind your design.  In this example, we suppose the entity at the
+Then, bind your design. In this example, we suppose the entity at the
 design apex is ``design``.
 
 ::
@@ -397,20 +397,20 @@ Using GRT from Ada
 
 .. warning::
   This topic is only for advanced users who know how to use `Ada`
-  and `GNAT`.  This is provided only for reference; we have tested
+  and `GNAT`. This is provided only for reference; we have tested
   this once before releasing `GHDL` 0.19, but this is not checked at
   each release.
 
 The simulator kernel of `GHDL` named :dfn:`GRT` is written in
 `Ada95` and contains a very light and slightly adapted version
-of `VHPI`.  Since it is an `Ada` implementation it is
+of `VHPI`. Since it is an `Ada` implementation it is
 called :dfn:`AVHPI`. Although being tough, you may interface to `AVHPI`.
 
 For using `AVHPI`, you need the sources of `GHDL` and to recompile
-them (at least the `GRT` library).  This library is usually compiled with
+them (at least the `GRT` library). This library is usually compiled with
 a `No_Run_Time` pragma, so that the user does not need to install the
-`GNAT` runtime library.  However, you certainly want to use the usual
-runtime library and want to avoid this pragma.  For this, reset the
+`GNAT` runtime library. However, you certainly want to use the usual
+runtime library and want to avoid this pragma. For this, reset the
 `GRT_PRAGMA_FLAG` variable.
 
 ::
@@ -420,7 +420,7 @@ runtime library and want to avoid this pragma.  For this, reset the
 
 Since `GRT` is a self-contained library, you don't want
 `gnatlink` to fetch individual object files (furthermore this
-doesn't always work due to tricks used in `GRT`).  For this,
+doesn't always work due to tricks used in `GRT`). For this,
 remove all the object files and make the :file:`.ali` files read-only.
 
 ::
@@ -429,7 +429,7 @@ remove all the object files and make the :file:`.ali` files read-only.
   $ chmod -w *.ali
 
 
-You may then install the sources files and the :file:`.ali` files.  I have never
+You may then install the sources files and the :file:`.ali` files. I have never
 tested this step.
 
 You are now ready to use it.
diff --git a/doc/references/ImplementationOfVITAL.rst b/doc/references/ImplementationOfVITAL.rst
index a3e0aeb98..77e7096c0 100644
--- a/doc/references/ImplementationOfVITAL.rst
+++ b/doc/references/ImplementationOfVITAL.rst
@@ -10,8 +10,8 @@ Implementation of VITAL
 
 .. index:: 1076.4
 
-This chapter describes how VITAL is implemented in GHDL.  Support of VITAL is
-really in a preliminary stage.  Do not expect too much of it as of right now.
+This chapter describes how VITAL is implemented in GHDL. Support of VITAL is
+really in a preliminary stage. Do not expect too much of it as of right now.
 
 .. _vital_packages:
 
@@ -21,9 +21,9 @@ VITAL packages
 The VITAL standard or IEEE 1076.4 was first published in 1995, and revised in
 2000.
 
-The version of the VITAL packages depends on the VHDL standard.  VITAL
+The version of the VITAL packages depends on the VHDL standard. VITAL
 1995 packages are used with the VHDL 1987 standard, while VITAL 2000
-packages are used with other standards.  This choice is based on the
+packages are used with other standards. This choice is based on the
 requirements of VITAL: VITAL 1995 requires the models follow the VHDL
 1987 standard, while VITAL 2000 requires the models follow VHDL 1993.
 
@@ -40,18 +40,18 @@ The VITAL standard (partially) implemented is the IEEE 1076.4 standard
 published in 1995.
 
 This standard defines restriction of the VHDL language usage on VITAL
-model.  A :dfn:`VITAL model` is a design unit (entity or architecture)
+model. A :dfn:`VITAL model` is a design unit (entity or architecture)
 decorated by the `VITAL_Level0` or `VITAL_Level1` attribute.
 These attributes are defined in the `ieee.VITAL_Timing` package.
 
-Currently, only VITAL level 0 checks are implemented.  VITAL level 1 models
+Currently, only VITAL level 0 checks are implemented. VITAL level 1 models
 can be analyzed, but GHDL doesn't check they comply with the VITAL standard.
 
 Moreover, GHDL doesn't check (yet) that timing generics are not read inside
 a VITAL level 0 model prior the VITAL annotation.
 
-The analysis of a non-conformant VITAL model fails.  You can disable the
-checks of VITAL restrictions with the *--no-vital-checks*.  Even when
+The analysis of a non-conformant VITAL model fails. You can disable the
+checks of VITAL restrictions with the *--no-vital-checks*. Even when
 restrictions are not checked, SDF annotation can be performed.
 
 .. _backannotation:
@@ -64,31 +64,31 @@ Backannotation
 :dfn:`Backannotation` is the process of setting VITAL generics with timing
 information provided by an external files.
 
-The external files must be SDF (Standard Delay Format) files.  GHDL
+The external files must be SDF (Standard Delay Format) files. GHDL
 supports a tiny subset of SDF version 2.1. Other version numbers can be
 used, provided no features added by later versions are used.
 
 Hierarchical instance names are not supported. However you can use a list of
-instances.  If there is no instance, the top entity will be annotated and
-the celltype must be the name of the top entity.  If there is at least one
+instances. If there is no instance, the top entity will be annotated and
+the celltype must be the name of the top entity. If there is at least one
 instance, the last instance name must be a component instantiation label, and
 the celltype must be the name of the component declaration instantiated.
 
-Instances being annotated are not required to be VITAL compliant.  However
+Instances being annotated are not required to be VITAL compliant. However
 generics being annotated must follow rules of VITAL (e.g., type must be a
 suitable vital delay type).
 
 Currently, only timing constraints applying on a timing generic of type
-`VitalDelayType01` has been implemented.  This SDF annotator is
-just a proof of concept.  Features will be added with the following GHDL
+`VitalDelayType01` has been implemented. This SDF annotator is
+just a proof of concept. Features will be added with the following GHDL
 release.
 
 Negative constraint calculation
 ===============================
 
 Negative constraint delay adjustments are necessary to handle negative
-constraints such as a negative setup time.  This step is defined in the VITAL
+constraints such as a negative setup time. This step is defined in the VITAL
 standard and should occur after backannotation.
 
-GHDL does not do negative constraint calculation.  It fails to handle models
-with negative constraint.  I hope to be able to add this phase soon.
+GHDL does not do negative constraint calculation. It fails to handle models
+with negative constraint. I hope to be able to add this phase soon.
diff --git a/doc/using/InvokingGHDL.rst b/doc/using/InvokingGHDL.rst
index de018d949..e64c695c6 100644
--- a/doc/using/InvokingGHDL.rst
+++ b/doc/using/InvokingGHDL.rst
@@ -59,7 +59,7 @@ Re-analyzes all the configurations, entities, architectures and package declarat
 	* an entity unit
 	* an entity unit followed by a name of an architecture unit
 
-Name of the units must be a simple name, without any dot.  You can select the name of the `WORK` library with the :option:`--work=NAME` option, as described in :ref:`GHDL:options`. See section :ref:`Top_entity`, for the restrictions on the root design of a hierarchy.
+Name of the units must be a simple name, without any dot. You can select the name of the `WORK` library with the :option:`--work=NAME` option, as described in :ref:`GHDL:options`. See section :ref:`Top_entity`, for the restrictions on the root design of a hierarchy.
 
 * If the GCC/LLVM backend was enabled during the compilation of GHDL, the elaboration command creates an executable containing the code of the VHDL sources, the elaboration code and simulation code to execute a design hierarchy. The executable is created in the current directory and the the filename is the name of the primary unit, or for the latter case, the concatenation of the name of the primary unit, a dash, and the name of the secondary unit (or architecture). Option :option:`-o` followed by a filename can override the default executable filename.
 
@@ -129,7 +129,7 @@ The advantages over the traditional approach (analyze and then elaborate) are:
 * This command produces a smaller executable, since unused units and subprograms do not generate code.
 
 .. HINT::
-   However, you should know that most of the time is spent in code generation and the analyze and elaborate command generates code for all units needed, even units of ``std`` and ``ieee`` libraries.  Therefore, according to the design, the time for this command may be higher than the time for the analyze command followed by the elaborate command.
+   However, you should know that most of the time is spent in code generation and the analyze and elaborate command generates code for all units needed, even units of ``std`` and ``ieee`` libraries. Therefore, according to the design, the time for this command may be higher than the time for the analyze command followed by the elaborate command.
 
 .. WARNING::
    This command is still under development. In case of problems, you should go back to the traditional way.
@@ -168,7 +168,7 @@ Make [``-m``]
 Analyze automatically outdated files and elaborate a design. The primary unit denoted by the ``primary`` argument must already be known by the system, either because you have already analyzed it (even if you have modified it) or because you have imported it. A file may be outdated because it has been modified (e.g. you have just edited it), or because a design unit contained in the file depends on a unit which is outdated. This rule is of course recursive.
 
 * With option :option:`--bind`, GHDL will stop before the final linking step. This is useful when the main entry point is not GHDL and you're linking GHDL object files into a foreign program.
-* With option :option:`-f` (force), GHDL analyzes all the units of the work library needed to create the design hierarchy. Outdated units are recompiled.  This is useful if you want to compile a design hierarchy with new compilation flags (for example, to add the *-g* debugging option).
+* With option :option:`-f` (force), GHDL analyzes all the units of the work library needed to create the design hierarchy. Outdated units are recompiled. This is useful if you want to compile a design hierarchy with new compilation flags (for example, to add the *-g* debugging option).
 
 The make command will only re-analyze design units in the work library. GHDL fails if it has to analyze an outdated unit from another library.
 
@@ -212,13 +212,13 @@ Options
 .. index:: IEEE 1076.3
 .. index:: 1076.3
 
-.. HINT:: Besides the options described below, `GHDL` passes any debugging options (those that begin with :option:`-g`) and optimizations options (those that begin with :option:`-O` or :option:`-f`) to `GCC`.  Refer to the `GCC` manual for details.
+.. HINT:: Besides the options described below, `GHDL` passes any debugging options (those that begin with :option:`-g`) and optimizations options (those that begin with :option:`-O` or :option:`-f`) to `GCC`. Refer to the `GCC` manual for details.
 
 .. index:: WORK library
 
 .. option:: --work<=NAME>
 
-  Specify the name of the ``WORK`` library.  Analyzed units are always placed in the library logically named ``WORK``.  With this option, you can set its name.  By default, the name is ``work``.
+  Specify the name of the ``WORK`` library. Analyzed units are always placed in the library logically named ``WORK``. With this option, you can set its name. By default, the name is ``work``.
 
   `GHDL` checks whether ``WORK`` is a valid identifier. Although being more or less supported, the ``WORK`` identifier should not be an extended identifier, since the filesystem may prevent it from working correctly (due to case sensitivity or forbidden characters in filenames).
 
@@ -226,13 +226,13 @@ Options
 
 .. option:: --workdir<=DIR>
 
-  Specify the directory where the ``WORK`` library is located. When this option is not present, the ``WORK`` library is in the current directory.  The object files created by the compiler are always placed in the same directory as the ``WORK`` library.
+  Specify the directory where the ``WORK`` library is located. When this option is not present, the ``WORK`` library is in the current directory. The object files created by the compiler are always placed in the same directory as the ``WORK`` library.
 
   Use option :option:`-P` to specify where libraries other than ``WORK`` are placed.
 
 .. option:: --std<=STD>
 
-  Specify the standard to use.  By default, the standard is ``93c``, which means VHDL-93 accepting VHDL-87 syntax.  For details on ``STD`` values see section :ref:`VHDL_standards`.
+  Specify the standard to use. By default, the standard is ``93c``, which means VHDL-93 accepting VHDL-87 syntax. For details on ``STD`` values see section :ref:`VHDL_standards`.
 
 .. option:: --ieee<=VER>
 
@@ -243,18 +243,18 @@ Options
   Select the ``IEEE`` library to use. ``VER`` must be one of:
 
   none
-    Do not supply an `IEEE` library.  Any library clause with the ``IEEE``
+    Do not supply an `IEEE` library. Any library clause with the ``IEEE``
     identifier will fail, unless you have created your own library with
     the `IEEE` name.
 
   standard
     Supply an `IEEE` library containing only packages defined by
-    ``ieee`` standards.  Currently, there are the multivalue logic system
+    ``ieee`` standards. Currently, there are the multivalue logic system
     package ``std_logic_1164`` defined by IEEE 1164, the synthesis
     packages ``numeric_bit`` and ``numeric_std`` defined by IEEE
     1076.3, and the ``vital`` packages ``vital_timing`` and
-    ``vital_primitives``, defined by IEEE 1076.4.  The version of these
-    packages is defined by the VHDL standard used.  See section :ref:`VITAL_packages`,
+    ``vital_primitives``, defined by IEEE 1076.4. The version of these
+    packages is defined by the VHDL standard used. See section :ref:`VITAL_packages`,
     for more details.
 
   synopsys
@@ -262,13 +262,13 @@ Options
     ``std_logic_arith``, ``std_logic_signed``,
     ``std_logic_unsigned``, ``std_logic_textio``.
 
-    These packages were created by some companies, and are popular.  However
+    These packages were created by some companies, and are popular. However
     they are not standard packages, and have been placed in the `IEEE`
     library without the permission from the ``ieee``.
 
   mentor
     Supply the standard packages and the following additional package:
-    ``std_logic_arith``.  This package is a slight variation of a definitely
+    ``std_logic_arith``. This package is a slight variation of a definitely
     not standard but widely misused package.
 
   To avoid errors, you must use the same `IEEE` library for all units of
@@ -277,7 +277,7 @@ Options
 .. option:: -P<DIRECTORY>
 
   Add `DIRECTORY` to the end of the list of directories to be searched for
-  library files.  A library is searched in `DIRECTORY` and also in
+  library files. A library is searched in `DIRECTORY` and also in
   `DIRECTORY/LIB/vVV` (where `LIB` is the name of the library and `VV`
   the vhdl standard).
 
@@ -289,13 +289,13 @@ Options
 
   When two operators are overloaded, give preference to the explicit declaration.
   This may be used to avoid the most common pitfall of the ``std_logic_arith``
-  package.  See section :ref:`IEEE_library_pitfalls`, for an example.
+  package. See section :ref:`IEEE_library_pitfalls`, for an example.
 
-.. WARNING:: This option is not set by default. I don't think this option is a good feature, because it breaks the encapsulation rule.  When set, an operator can be silently overridden in another package.  You'd do better to fix your design and use the ``numeric_std`` package.
+.. WARNING:: This option is not set by default. I don't think this option is a good feature, because it breaks the encapsulation rule. When set, an operator can be silently overridden in another package. You'd do better to fix your design and use the ``numeric_std`` package.
 
 .. option:: -frelaxed-rules
 
-  Within an object declaration, allow references to the name (which references the hidden declaration).  This ignores the error in the following code:
+  Within an object declaration, allow references to the name (which references the hidden declaration). This ignores the error in the following code:
 
   .. code-block:: VHDL
 
@@ -316,7 +316,7 @@ Options
 
 .. option:: -fpsl
 
-  Enable parsing of PSL assertions within comments.  See section :ref:`PSL_implementation` for more details.
+  Enable parsing of PSL assertions within comments. See section :ref:`PSL_implementation` for more details.
 
 .. option:: --no-vital-checks
 .. option:: --vital-checks
@@ -350,11 +350,11 @@ Some constructions are not erroneous but dubious. Warnings are diagnostic messag
 
 .. option:: --warn-default-binding
 
-  During analyze, warns if a component instantiation has neither configuration specification nor default binding.  This may be useful if you want to detect during analyze possibly unbound components if you don't use configuration. See section :ref:`VHDL_standards` for more details about default binding rules.
+  During analyze, warns if a component instantiation has neither configuration specification nor default binding. This may be useful if you want to detect during analyze possibly unbound components if you don't use configuration. See section :ref:`VHDL_standards` for more details about default binding rules.
 
 .. option:: --warn-binding
 
-  During elaboration, warns if a component instantiation is not bound (and not explicitly left unbound).  Also warns if a port of an entity is not bound in a configuration specification or in a component configuration. This warning is enabled by default, since default binding rules are somewhat complex and an unbound component is most often unexpected.
+  During elaboration, warns if a component instantiation is not bound (and not explicitly left unbound). Also warns if a port of an entity is not bound in a configuration specification or in a component configuration. This warning is enabled by default, since default binding rules are somewhat complex and an unbound component is most often unexpected.
 
   However, warnings are still emitted if a component instantiation is inside a generate statement. As a consequence, if you use the conditional generate statement to select a component according to the implementation, you will certainly get warnings.
 
@@ -364,18 +364,18 @@ Some constructions are not erroneous but dubious. Warnings are diagnostic messag
 
 .. option:: --warn-vital-generic
 
-  Warns if a generic name of a vital entity is not a vital generic name.  This
+  Warns if a generic name of a vital entity is not a vital generic name. This
   is set by default.
 
 .. option:: --warn-delayed-checks
 
-  Warns for checks that cannot be done during analysis time and are postponed to elaboration time.  This is because not all procedure bodies are available during analysis (either because a package body has not yet been analysed or because `GHDL` doesn't read not required package bodies).
+  Warns for checks that cannot be done during analysis time and are postponed to elaboration time. This is because not all procedure bodies are available during analysis (either because a package body has not yet been analysed or because `GHDL` doesn't read not required package bodies).
 
   These are checks for no wait statements in a procedure called in a sensitized process and checks for pure rules of a function.
 
 .. option:: --warn-body
 
-  Emit a warning if a package body which is not required is analyzed.  If a package does not declare a subprogram or a deferred constant, the package does not require a body.
+  Emit a warning if a package body which is not required is analyzed. If a package does not declare a subprogram or a deferred constant, the package does not require a body.
 
 .. option:: --warn-specs
 
@@ -468,7 +468,7 @@ Copy [``--copy``]
 
 .. option:: --copy <--work=name [options]>
 
-Make a local copy of an existing library.  This is very useful if you want to add units to the ``ieee`` library:
+Make a local copy of an existing library. This is very useful if you want to add units to the ``ieee`` library:
 
 .. code-block:: shell
 
@@ -627,9 +627,9 @@ When you analyze this design, GHDL does not accept it (two long lines have been
       [std_logic_vector, std_logic_vector return boolean]
   ../translate/ghdldrv/ghdl: compilation error
 
-Indeed, the `"="` operator is defined in both packages, and both are visible at the place it is used.  The first declaration is an implicit one, which occurs when the `std_logic_vector` type is declared and is an element to element comparison.  The second one is an explicit declared function, with the semantics of an unsigned comparison.
+Indeed, the `"="` operator is defined in both packages, and both are visible at the place it is used. The first declaration is an implicit one, which occurs when the `std_logic_vector` type is declared and is an element to element comparison. The second one is an explicit declared function, with the semantics of an unsigned comparison.
 
-With some analysers, the explicit declaration has priority over the implicit declaration, and this design can be analyzed without error.  However, this is not the rule given by the VHDL LRM, and since GHDL follows these rules,
+With some analysers, the explicit declaration has priority over the implicit declaration, and this design can be analyzed without error. However, this is not the rule given by the VHDL LRM, and since GHDL follows these rules,
 it emits an error.
 
 You can force GHDL to use this rule with the *-fexplicit* option (see :ref:`GHDL:options` for further details). However it is easy to fix this error, by using a selected name:
diff --git a/doc/using/QuickStartGuide.rst b/doc/using/QuickStartGuide.rst
index 9dbe84bdf..974d550ac 100644
--- a/doc/using/QuickStartGuide.rst
+++ b/doc/using/QuickStartGuide.rst
@@ -47,7 +47,7 @@ To illustrate the general purpose of `VHDL`, here is a commented `'Hello world'`
 .. HINT::
    If a GCC/LLVM variant of `GHDL` is used:
 
-   * `Analysis` generates a file, :file:`hello.o`, which is the object file corresponding to your `VHDL` program.  This is not created with mcode.
+   * `Analysis` generates a file, :file:`hello.o`, which is the object file corresponding to your `VHDL` program. This is not created with mcode.
    * The elaboration step is mandatory after running the analysis and prior to launching the simulation. This wil generate an executable binary named :file:`hello_world`.
    * As a result, :option:`-r` is just a passthrough to the binary generated in the `elaboration`. Therefore, the executable can be run directly, ``./hello_world``. See :option:`-r` for more informartion.
 
@@ -96,7 +96,7 @@ VHDL is generally used for hardware design. This example starts with a `full add
     co <= (i0 and i1) or (i0 and ci) or (i1 and ci);
   end rtl;
 
-You can analyze this design file, ``ghdl -a adder.vhdl``, and try to execute the `adder` design. But this is useless, since nothing externally visible will happen. In order to check this full adder, a :dfn:`testbench` has to be run. This testbench is very simple, since the adder is also simple: it checks exhaustively all inputs.  Note that only the behaviour is tested, timing constraints are not checked. A file named :file:`adder_tb.vhdl` contains the testbench for the adder:
+You can analyze this design file, ``ghdl -a adder.vhdl``, and try to execute the `adder` design. But this is useless, since nothing externally visible will happen. In order to check this full adder, a :dfn:`testbench` has to be run. This testbench is very simple, since the adder is also simple: it checks exhaustively all inputs. Note that only the behaviour is tested, timing constraints are not checked. A file named :file:`adder_tb.vhdl` contains the testbench for the adder:
 
 .. code-block:: VHDL
 
@@ -181,14 +181,14 @@ Unless you are only studying VHDL, you will work with larger designs than the on
 
 - First, untar the sources: ``tar zxvf dlx.tar.gz``.
 
-.. HINT:: In order not to pollute the sources with the library, it is a good idea to create a :file:`work/` subdirectory for the `WORK` library.  To any GHDL commands, we will add the :option:`--workdir=work` option, so that all files generated by the compiler (except the executable) will be placed in this directory.
+.. HINT:: In order not to pollute the sources with the library, it is a good idea to create a :file:`work/` subdirectory for the `WORK` library. To any GHDL commands, we will add the :option:`--workdir=work` option, so that all files generated by the compiler (except the executable) will be placed in this directory.
 
   .. code-block:: shell
 
      $ cd dlx
      $ mkdir work
 
-* Then, we will run the ``dlx_test_behaviour`` design.  We need to analyze all the design units for the design hierarchy, in the correct order. GHDL provides an easy way to do this, by importing the sources, ``ghdl -i --workdir=work *.vhdl``.
+* Then, we will run the ``dlx_test_behaviour`` design. We need to analyze all the design units for the design hierarchy, in the correct order. GHDL provides an easy way to do this, by importing the sources, ``ghdl -i --workdir=work *.vhdl``.
 
 * GHDL knows all the design units of the DLX, but none of them has been analyzed. Run the make option, ``ghdl -m --workdir=work dlx_test_behaviour``, which analyzes and elaborates a design. This creates many files in the :file:`work/` directory, and (GCC/LLVM only) the :file:`dlx_test_behaviour` executable in the current directory.
 
@@ -201,7 +201,7 @@ Unless you are only studying VHDL, you will work with larger designs than the on
      dlx-behaviour.vhdl:395:11:(assertion note): TRAP instruction
       encountered, execution halted
 
-* Lastly, since the clock is still running, you have to manually stop the program with the :kbd:`C-c` key sequence.  This behavior prevents you from running the test bench in batch mode. However, you may force the simulator to stop when an assertion above or equal a certain severity level occurs. To do so, call run with this option instead: ``ghdl -r --workdir=work dlx_test_behaviour --assert-level=note```. With this option, the program stops just after the previous message:
+* Lastly, since the clock is still running, you have to manually stop the program with the :kbd:`C-c` key sequence. This behavior prevents you from running the test bench in batch mode. However, you may force the simulator to stop when an assertion above or equal a certain severity level occurs. To do so, call run with this option instead: ``ghdl -r --workdir=work dlx_test_behaviour --assert-level=note```. With this option, the program stops just after the previous message:
 
   .. code-block:: shell
 
diff --git a/doc/using/Simulation.rst b/doc/using/Simulation.rst
index 570c184af..8bb43b941 100644
--- a/doc/using/Simulation.rst
+++ b/doc/using/Simulation.rst
@@ -10,11 +10,11 @@ Simulation options
 ==================
 
 In most system environments, it is possible to pass options while
-invoking a program.  Contrary to most programming languages, there is no
+invoking a program. Contrary to most programming languages, there is no
 standard method in VHDL to obtain the arguments or to set the exit
 status.
 
-In GHDL, it is impossible to pass parameters to your design.  A later version
+In GHDL, it is impossible to pass parameters to your design. A later version
 could do it through the generic interfaces of the top entity.
 
 However, the GHDL runtime behaviour can be modified with some options; for
@@ -24,14 +24,14 @@ The exit status of the simulation is ``EXIT_SUCCESS`` (0) if the
 simulation completes, or ``EXIT_FAILURE`` (1) in case of error
 (assertion failure, overflow or any constraint error).
 
-Here is the list of the most useful options.  Some debugging options are
-also available, but not described here.  The :option:`--help` option lists
+Here is the list of the most useful options. Some debugging options are
+also available, but not described here. The :option:`--help` option lists
 all options available, including the debugging one.
 
 .. option:: --assert-level<=LEVEL>
 
   Select the assertion level at which an assertion violation stops the
-  simulation.  `LEVEL` is the name from the `severity_level`
+  simulation. `LEVEL` is the name from the `severity_level`
   enumerated type defined in the `standard` package or the
   ``none`` name.
 
@@ -58,8 +58,8 @@ all options available, including the debugging one.
 
 .. option:: --stop-time<=TIME>
 
-  Stop the simulation after ``TIME``.  ``TIME`` is expressed as a time
-  value, *without* any space.  The time is the simulation time, not
+  Stop the simulation after ``TIME``. ``TIME`` is expressed as a time
+  value, *without* any space. The time is the simulation time, not
   the real clock time.
 
   For example::
@@ -86,8 +86,8 @@ all options available, including the debugging one.
   Do VITAL annotation on `PATH` with SDF file :file:`FILENAME`.
 
   `PATH` is a path of instances, separated with ``.`` or ``/``.
-  Any separator can be used.  Instances are component instantiation labels,
-  generate labels or block labels.  Currently, you cannot use an indexed name.
+  Any separator can be used. Instances are component instantiation labels,
+  generate labels or block labels. Currently, you cannot use an indexed name.
 
   Specifying a delay::
 
@@ -97,7 +97,7 @@ all options available, including the debugging one.
 
   If the option contains a type of delay, that is ``min=``,
   ``typ=`` or ``max=``, the annotator use respectively minimum,
-  typical or maximum values.  If the option does not contain a type of delay,
+  typical or maximum values. If the option does not contain a type of delay,
   the annotator uses the typical delay.
 
   See section :ref:`Backannotation`, for more details.
@@ -169,19 +169,19 @@ Export waveforms
   .. index:: dump of signals
 
   Option :option:`--vcd` dumps into the VCD file `FILENAME` the signal
-  values before each non-delta cycle.  If `FILENAME` is ``-``,
+  values before each non-delta cycle. If `FILENAME` is ``-``,
   then the standard output is used, otherwise a file is created or
   overwritten.
 
   The :option:`--vcdgz` option is the same as the *--vcd* option,
   but the output is compressed using the `zlib` (`gzip`
-  compression).  However, you can't use the ``-`` filename.
+  compression). However, you can't use the ``-`` filename.
   Furthermore, only one VCD file can be written.
 
   :dfn:`VCD` (value change dump) is a file format defined
   by the `verilog` standard and used by virtually any wave viewer.
 
-  Since it comes from `verilog`, only a few VHDL types can be dumped.  GHDL
+  Since it comes from `verilog`, only a few VHDL types can be dumped. GHDL
   dumps only signals whose base type is of the following:
 
   * types defined in the ``std.standard`` package:
@@ -204,7 +204,7 @@ Export waveforms
   dumped, which can generate big files.
 
   It is very unfortunate there is no standard or well-known wave file
-  format supporting VHDL types.  If you are aware of such a free format,
+  format supporting VHDL types. If you are aware of such a free format,
   please mail me (:ref:`Reporting_bugs`).
 
 .. option:: --vcd-nodate
@@ -219,12 +219,12 @@ Export waveforms
 
 .. option:: --wave<=FILENAME>
 
-  Write the waveforms into a `ghw` (GHdl Waveform) file.  Currently, all
+  Write the waveforms into a `ghw` (GHdl Waveform) file. Currently, all
   the signals are dumped into the waveform file, you cannot select a hierarchy
   of signals to be dumped.
 
   The format of this file was defined by myself and is not yet completely fixed.
-  It may change slightly.  The ``gtkwave`` tool can read the GHW files.
+  It may change slightly. The ``gtkwave`` tool can read the GHW files.
 
   Contrary to VCD files, any VHDL type can be dumped into a GHW file.
 
@@ -239,7 +239,7 @@ Export hierarchy and references
   This may be useful to understand the structure of a complex
   design. `KIND` is optional, but if set must be one of:
 
-  * ``none`` Do not display hierarchy.  Same as if the option was not present.
+  * ``none`` Do not display hierarchy. Same as if the option was not present.
 
   * ``inst`` Display entities, architectures, instances, blocks and generates statements.