Rephrase documentation - typos, grammatical nuance, and links

3 files changed, 208 insertions, 209 deletions

diff --git a/doc/using/InvokingGHDL.rst b/doc/using/InvokingGHDL.rst
index dd50a5874..931b1115e 100644
--- a/doc/using/InvokingGHDL.rst
+++ b/doc/using/InvokingGHDL.rst
@@ -13,10 +13,10 @@ The form of the :program:`ghdl` command is ``ghdl command [options...]``. There
    If the number of options is large and the command line length is beyond the system limit, you can use a response file. An argument that starts with a ``@`` is considered as a response file; it is replaced by arguments read from the file (separated by blanks and end of line).
 
 .. HINT::
-   Only the most common commands and options are shown here. For most advanced and experimental features see section :ref:`REF:Command`.
+   Only the most common commands and options are shown here. For the most advanced and experimental features see section :ref:`REF:Command`.
 
 .. WARNING::
-   During analysis and elaboration GHDL may read the ``std`` and ``ieee`` files. The location of these files is based on the prefix, which is (in priority order):
+   During analysis and elaboration GHDL may read the ``std`` and ``ieee`` files. The location of these files is based on the prefix, which is (in order of priority):
 
 	* the :option:`--PREFIX` command line option
 	* the :envvar:`GHDL_PREFIX` environment variable
@@ -27,7 +27,7 @@ The form of the :program:`ghdl` command is ``ghdl command [options...]``. There
 Design building commands
 ========================
 
-The mostly used commands of GHDL are those to analyze and elaborate a design.
+The most commonly used commands of GHDL are those to analyze and elaborate a design.
 
 
 .. index:: cmd analysis
@@ -39,17 +39,19 @@ Analysis [``-a``]
 
 Analyzes/compiles one or more files, and creates an object file for each source file. Any argument starting with a dash is an option, the others are filenames. No options are allowed after a filename argument. GHDL analyzes each filename in the given order, and stops the analysis in case of error (remaining files are not analyzed).
 
-See :ref:`GHDL_options`, for details on the GHDL options. For example, to produce debugging information such as line numbers, use: ``ghdl -a -g my_design.vhdl``.
+See ':ref:`GHDL:options`', for details on the GHDL options. For example, to produce debugging information such as line numbers, use: ``ghdl -a -g my_design.vhdl``.
 
 
 .. index:: cmd elaboration
 
+.. _Elaboration:command:
+
 Elaboration [``-e``]
 ------------------------
 
 .. option:: -e <[options...] primary_unit [secondary_unit]>
 
-Re-analyzes all the configurations, entities, architectures and package declarations, and creates the default configurations and the default binding indications according to the LRM rules. It also generates the list of objects files required for the executable. Then, it links all these files with the runtime library. The actual elaboration is performed at runtime.
+Re-analyzes all the configurations, entities, architectures and package declarations, and creates the default configurations and the default binding indications according to the LRM rules. It also generates the list of object files required for the executable. Then, it links all these files with the runtime library. The actual elaboration is performed at runtime.
 
 * The elaboration command, :option:`-e`, must be followed by a name of either:
 
@@ -57,11 +59,11 @@ Re-analyzes all the configurations, entities, architectures and package declarat
 	* an entity unit
 	* an entity unit followed by a name of an architecture unit
 
-Name of the units must be a simple name, without any dot.  You can select the name of the `WORK` library with the :option:`--work=NAME` option, as described in :ref:`GHDL_options`. See section ':ref:`Top_entity`', for the restrictions on the root design of a hierarchy.
+Name of the units must be a simple name, without any dot.  You can select the name of the `WORK` library with the :option:`--work=NAME` option, as described in ':ref:`GHDL:options`'. See section ':ref:`Top_entity`', for the restrictions on the root design of a hierarchy.
 
-* If the GCC/LLVM backend was enabled during the compilation of GHDL, the elaboration command creates an executable containing the code of the VHDL sources, the elaboration code and simulation code to execute a design hierarchy. The executable is created in the current directory and the the filename is the name of the primary unit, or for the later case, the concatenation of the name of the primary unit, a dash, and the name of the secondary unit (or architecture). Option :option:`-o` followed by a filename can override the default executable filename.
+* If the GCC/LLVM backend was enabled during the compilation of GHDL, the elaboration command creates an executable containing the code of the VHDL sources, the elaboration code and simulation code to execute a design hierarchy. The executable is created in the current directory and the the filename is the name of the primary unit, or for the latter case, the concatenation of the name of the primary unit, a dash, and the name of the secondary unit (or architecture). Option :option:`-o` followed by a filename can override the default executable filename.
 
-* If mcode is used, this command elaborates the design but does not generate anything. Since the run command also elaborates the design, this con be skipped.
+* If mcode is used, this command elaborates the design but does not generate anything. Since the run command also elaborates the design, this can be skipped.
 
 
 .. index:: cmd run
@@ -124,10 +126,10 @@ The advantages over the traditional approach (analyze and then elaborate) are:
 * The compilation cycle is achieved in one command.
 * Since the files are only parsed once, the compilation cycle may be faster.
 * You don't need to know an analysis order.
-* This command produces smaller executable, since unused units and subprograms do not generate code.
+* This command produces a smaller executable, since unused units and subprograms do not generate code.
 
 .. HINT::
-   However, you should know that currently most of the time is spent in code generation and the analyze and elaborate command generate code for all units needed, even units of ``std`` and ``ieee`` libraries.  Therefore, according to the design, the time for this command may be higher than the time for the analyze command followed by the elaborate command.
+   However, you should know that most of the time is spent in code generation and the analyze and elaborate command generates code for all units needed, even units of ``std`` and ``ieee`` libraries.  Therefore, according to the design, the time for this command may be higher than the time for the analyze command followed by the elaborate command.
 
 .. WARNING::
    This command is still under development. In case of problems, you should go back to the traditional way.
@@ -136,7 +138,7 @@ The advantages over the traditional approach (analyze and then elaborate) are:
 Design rebuilding commands
 ==========================
 
-Analyzing and elaborating a design consisting in several files can be tricky, due to dependencies. GHDL has a few commands to rebuild a design.
+Analyzing and elaborating a design consisting of several files can be tricky, due to dependencies. GHDL has a few commands to rebuild a design.
 
 
 .. index:: cmd importing files
@@ -146,7 +148,7 @@ Import [``-i``]
 
 .. option:: -i <[options] file...>
 
-All the files specified in the command line are scanned, parsed and added in the libraries but as not yet analyzed. No object files are created. It's purpose is to localize design units in the design files. The make command will then be able to recursively build a hierarchy from an entity name or a configuration name.
+All the files specified in the command line are scanned, parsed and added into the libraries but as not yet analyzed. No object files are created. Its purpose is to localize design units in the design files. The make command will then be able to recursively build a hierarchy from an entity name or a configuration name.
 
 .. HINT::
 
@@ -163,14 +165,14 @@ Make [``-m``]
 
 .. option:: -m <[options] primary [secondary]>
 
-Analyze automatically outdated files and elaborate a design. The primary unit denoted by the ``primary`` argument must already be known by the system, either because you have already analyzed it (even if you have modified it) or because you have imported it. A file may be outdated because it has been modified (e.g. you just have edited it), or because a design unit contained in the file depends on a unit which is outdated. This rule is of course recursive.
+Analyze automatically outdated files and elaborate a design. The primary unit denoted by the ``primary`` argument must already be known by the system, either because you have already analyzed it (even if you have modified it) or because you have imported it. A file may be outdated because it has been modified (e.g. you have just edited it), or because a design unit contained in the file depends on a unit which is outdated. This rule is of course recursive.
 
 * With option :option:`--bind`, GHDL will stop before the final linking step. This is useful when the main entry point is not GHDL and you're linking GHDL object files into a foreign program.
-* With option :option:`-f` (force), GHDL analyzes all the units of the work library needed to create the design hierarchy. Not outdated units are recompiled.  This is useful if you want to compile a design hierarchy with new compilation flags (for example, to add the *-g* debugging option).
+* With option :option:`-f` (force), GHDL analyzes all the units of the work library needed to create the design hierarchy. Outdated units are recompiled.  This is useful if you want to compile a design hierarchy with new compilation flags (for example, to add the *-g* debugging option).
 
 The make command will only re-analyze design units in the work library. GHDL fails if it has to analyze an outdated unit from another library.
 
-The purpose of this command is to be able to compile a design without prior knowledge of file order. In the VHDL model, some units must be analyzed before others (e.g. an entity before its architecture). It might be a nightmare to analyze a full design of several files, if you don't have the ordered list of file. This command computes an analysis order.
+The purpose of this command is to be able to compile a design without prior knowledge of file order. In the VHDL model, some units must be analyzed before others (e.g. an entity before its architecture). It might be a nightmare to analyze a full design of several files if you don't have the ordered list of files. This command computes an analysis order.
 
 The make command fails when a unit was not previously parsed. For example, if you split a file containing several design units into several files, you must either import these new files or analyze them so that GHDL knows in which file these units are.
 
@@ -200,6 +202,8 @@ Generate a Makefile containing only dependencies to build a design unit.
 This command works like the make and gen-makefile commands (see :option:`-m`), but instead of a full makefile only dependencies without rules are generated on the standard output.
 Theses rules can then be integrated in another Makefile.
 
+.. _GHDL:options:
+
 Options
 =======
 
@@ -216,9 +220,9 @@ Options
 
   Specify the name of the ``WORK`` library.  Analyzed units are always placed in the library logically named ``WORK``.  With this option, you can set its name.  By default, the name is ``work``.
 
-  `GHDL` checks whether ``WORK`` is a valid identifier. Although being more or less supported, the ``WORK`` identifier should not be an extended identifier, since the filesystem may prevent it from correctly working (due to case sensitivity or forbidden characters in filenames).
+  `GHDL` checks whether ``WORK`` is a valid identifier. Although being more or less supported, the ``WORK`` identifier should not be an extended identifier, since the filesystem may prevent it from working correctly (due to case sensitivity or forbidden characters in filenames).
 
-  `VHDL` rules forbid you to add units to the ``std`` library. Furthermore, you should not put units in the ``ieee`` library.
+  `VHDL` rules forbid you from adding units to the ``std`` library. Furthermore, you should not put units in the ``ieee`` library.
 
 .. option:: --workdir<=DIR>
 
@@ -240,14 +244,14 @@ Options
 
   none
     Do not supply an `IEEE` library.  Any library clause with the ``IEEE``
-    identifier will fail, unless you have created by your own a library with
+    identifier will fail, unless you have created your own library with
     the `IEEE` name.
 
   standard
     Supply an `IEEE` library containing only packages defined by
     ``ieee`` standards.  Currently, there are the multivalue logic system
-    packages ``std_logic_1164`` defined by IEEE 1164, the synthesis
-    packages , ``numeric_bit`` and ``numeric_std`` defined by IEEE
+    package ``std_logic_1164`` defined by IEEE 1164, the synthesis
+    packages ``numeric_bit`` and ``numeric_std`` defined by IEEE
     1076.3, and the ``vital`` packages ``vital_timing`` and
     ``vital_primitives``, defined by IEEE 1076.4.  The version of these
     packages is defined by the VHDL standard used.  See section ':ref:`VITAL_packages`',
@@ -264,8 +268,8 @@ Options
 
   mentor
     Supply the standard packages and the following additional package:
-    ``std_logic_arith``.  The package is a slight variation of a definitely
-    not standard but widely mis-used package.
+    ``std_logic_arith``.  This package is a slight variation of a definitely
+    not standard but widely misused package.
 
   To avoid errors, you must use the same `IEEE` library for all units of
   your design, and during elaboration.
@@ -287,26 +291,26 @@ Options
   This may be used to avoid the most common pitfall of the ``std_logic_arith``
   package.  See section ':ref:`IEEE_library_pitfalls`', for an example.
 
-.. WARNING:: This option is not set by default. I don't think this option is a good feature, because it breaks the encapsulation rule.  When set, an operator can be silently overridden in another package.  You'd better fix your design and use the ``numeric_std`` package.
+.. WARNING:: This option is not set by default. I don't think this option is a good feature, because it breaks the encapsulation rule.  When set, an operator can be silently overridden in another package.  You'd do better to fix your design and use the ``numeric_std`` package.
 
 .. option:: -frelaxed-rules
 
-  Within an object declaration, allow to reference the name (which references the hidden declaration).  This ignores the error in the following code:
+  Within an object declaration, allow references to the name (which references the hidden declaration).  This ignores the error in the following code:
 
   .. code-block:: VHDL
 
-    package pkg1 is
-     type state is (state1, state2, state3);
-    end pkg1;
+   package pkg1 is
+      type state is (state1, state2, state3);
+   end pkg1;
 
-    use work.pkg1.all;
-    package pkg2 is
-     constant state1 : state := state1;
-    end pkg2;
+   use work.pkg1.all;
+   package pkg2 is
+      constant state1 : state := state1;
+   end pkg2;
 
   Some code (such as Xilinx packages) have such constructs, which are valid.
 
-  (The scope of the ``state1`` constant start at the `constant` word. Because the constant ``state1`` and the enumeration literal ``state1`` are homograph, the enumeration literal is hidden in the immediate scope of the constant).
+  (The scope of the ``state1`` constant starts at the `constant` keyword. Because the constant ``state1`` and the enumeration literal ``state1`` are homographs, the enumeration literal is hidden in the immediate scope of the constant).
 
   This option also relaxes the rules about pure functions. Violations result in warnings instead of errors.
 
@@ -338,7 +342,7 @@ Warnings
 Some constructions are not erroneous but dubious. Warnings are diagnostic messages that report such constructions. Some warnings are reported only during analysis, others during elaboration.
 
 .. HINT::
-   You could disable a warning by using the ``--warn-no-XXX`` or ``-Wno-XX`` instead of ``--warn-XXX`` or ``-WXXX``.
+   You could disable a warning by using the ``--warn-no-XXX`` or ``-Wno-XXX`` instead of ``--warn-XXX`` or ``-WXXX``.
 
 .. option:: --warn-reserved
 
@@ -346,13 +350,13 @@ Some constructions are not erroneous but dubious. Warnings are diagnostic messag
 
 .. option:: --warn-default-binding
 
-  During analyze, warns if a component instantiation has neither configuration specification nor default binding.  This may be useful if you want to detect during analyze possibly unbound component if you don't use configuration. See section ':ref:`VHDL_standards`' for more details about default binding rules.
+  During analyze, warns if a component instantiation has neither configuration specification nor default binding.  This may be useful if you want to detect during analyze possibly unbound components if you don't use configuration. See section ':ref:`VHDL_standards`' for more details about default binding rules.
 
 .. option:: --warn-binding
 
   During elaboration, warns if a component instantiation is not bound (and not explicitly left unbound).  Also warns if a port of an entity is not bound in a configuration specification or in a component configuration. This warning is enabled by default, since default binding rules are somewhat complex and an unbound component is most often unexpected.
 
-  However, warnings are even emitted if a component instantiation is inside a generate statement. As a consequence, if you use the conditional generate statement to select a component according to the implementation, you will certainly get warnings.
+  However, warnings are still emitted if a component instantiation is inside a generate statement. As a consequence, if you use the conditional generate statement to select a component according to the implementation, you will certainly get warnings.
 
 .. option:: --warn-library
 
@@ -367,7 +371,7 @@ Some constructions are not erroneous but dubious. Warnings are diagnostic messag
 
   Warns for checks that cannot be done during analysis time and are postponed to elaboration time.  This is because not all procedure bodies are available during analysis (either because a package body has not yet been analysed or because `GHDL` doesn't read not required package bodies).
 
-  These are checks for no wait statement in a procedure called in a sensitized process and checks for pure rules of a function.
+  These are checks for no wait statements in a procedure called in a sensitized process and checks for pure rules of a function.
 
 .. option:: --warn-body
 
@@ -391,7 +395,7 @@ Some constructions are not erroneous but dubious. Warnings are diagnostic messag
 
 .. option:: --warn-parenthesis
 
-  Emit a warning in case of weird use of parenthesis
+  Emit a warning in case of weird use of parentheses.
 
 .. option:: --warn-runtime-error
 
@@ -410,7 +414,7 @@ Diagnostics Control
 .. option:: -fdiagnostics-show-option
 .. option:: -fno-diagnostics-show-option
 
-  Control whether the warning option is displayed at the end of warning messages, so that user can easily know how to disable it.
+  Control whether the warning option is displayed at the end of warning messages, so that the user can easily know how to disable it.
 
 
 Library commands
@@ -453,7 +457,7 @@ Remove [``--remove``]
 
 .. option:: --remove <[options]>
 
-Do like the clean command but remove the library too. Note that after removing a design library, the files are not
+Acts like the clean command but removes the library too. Note that after removing a design library, the files are not
 known anymore by GHDL.
 
 
@@ -464,7 +468,7 @@ Copy [``--copy``]
 
 .. option:: --copy <--work=name [options]>
 
-Make a local copy of an existing library.  This is very useful if you want to add unit to the ``ieee`` library:
+Make a local copy of an existing library.  This is very useful if you want to add units to the ``ieee`` library:
 
 .. code-block:: shell
 
@@ -475,7 +479,7 @@ Make a local copy of an existing library.  This is very useful if you want to ad
 VPI build commands
 ==================
 
-These commands simplify the compile and the link of a user vpi module. They are all wrapper: the arguments are in fact a whole command line that is executed with additional switches. Currently a unix-like compiler (like `cc`, `gcc` or `clang`) is expected: the additional switches use their syntax. The only option is `-v` which displays the
+These commands simplify the compile and the link of a user vpi module. They are all wrappers: the arguments are in fact a whole command line that is executed with additional switches. Currently a unix-like compiler (like `cc`, `gcc` or `clang`) is expected: the additional switches use their syntax. The only option is `-v` which displays the
 command before its execution.
 
 
@@ -486,7 +490,7 @@ compile [``--vpi-compile``]
 
 .. option:: --vpi-compile <command>
 
-Add include path to the command and execute it::
+Add an include path to the command and execute it::
 
   ghdl --vpi-compile command
 
@@ -511,7 +515,7 @@ link [``--vpi-link``]
 
 .. option:: --vpi-link <command>
 
-Add library path and name to the command and execute it::
+Add a library path and name to the command and execute it::
 
   ghdl --vpi-link command
 
@@ -572,46 +576,45 @@ Display the library directory added by the link flags.
 IEEE library pitfalls
 =====================
 
-When you use options :option:`--ieee=synopsys` or :option:`--ieee=mentor`, the ``ieee`` library contains non standard packages such as ``std_logic_arith``. These packages are not standard because there are not described by an IEEE standard, even if they have been put in the `IEEE` library. Furthermore, they are not really de-facto standard, because there are slight differences between the packages of Mentor and those of Synopsys. Furthermore, since they are not well-thought, their use has pitfalls. For example, this description has error during compilation:
+When you use options :option:`--ieee=synopsys` or :option:`--ieee=mentor`, the ``ieee`` library contains non standard packages such as ``std_logic_arith``. These packages are not standard because there are not described by an IEEE standard, even if they have been put in the `IEEE` library. Furthermore, they are not really de-facto standard, because there are slight differences between the packages of Mentor and those of Synopsys. Furthermore, since they are not well thought out, their use has pitfalls. For example, this description has an error during compilation:
 
 .. code-block:: VHDL
 
-  library ieee;
-  use ieee.std_logic_1164.all;
-
-  --  A counter from 0 to 10.
-  entity counter is
-     port (val : out std_logic_vector (3 downto 0);
-           ck : std_logic;
-           rst : std_logic);
-  end counter;
-
-  library ieee;
-  use ieee.std_logic_unsigned.all;
-
-  architecture bad of counter
-  is
-     signal v : std_logic_vector (3 downto 0);
-  begin
-     process (ck, rst)
-     begin
-       if rst = '1' then
-          v <= x"0";
-       elsif rising_edge (ck) then
-          if v = "1010" then -- Error
-             v <= x"0";
-          else
-             v <= v + 1;
-          end if;
-       end if;
-     end process;
-
-     val <= v;
-  end bad;
-
-
-When you analyze this design, GHDL does not accept it (too long lines
-have been split for readability):
+   library ieee;
+   use ieee.std_logic_1164.all;
+
+   --  A counter from 0 to 10.
+   entity counter is
+      port (val : out std_logic_vector (3 downto 0);
+            ck : std_logic;
+            rst : std_logic);
+   end counter;
+
+   library ieee;
+   use ieee.std_logic_unsigned.all;
+
+   architecture bad of counter
+   is
+      signal v : std_logic_vector (3 downto 0);
+   begin
+      process (ck, rst)
+      begin
+        if rst = '1' then
+           v <= x"0";
+        elsif rising_edge (ck) then
+           if v = "1010" then -- Error
+              v <= x"0";
+           else
+              v <= v + 1;
+           end if;
+        end if;
+      end process;
+
+      val <= v;
+   end bad;
+
+
+When you analyze this design, GHDL does not accept it (two long lines have been split for readability):
 
 .. code-block:: shell
 
@@ -624,64 +627,64 @@ have been split for readability):
       [std_logic_vector, std_logic_vector return boolean]
   ../translate/ghdldrv/ghdl: compilation error
 
-Indeed, the `"="` operator is defined in both packages, and both are visible at the place it is used.  The first declaration is an implicit one, which occurs when the `std_logic_vector` type is declared and is an element to element comparison, the second one is an explicit declared function, with the semantic of an unsigned comparison.
+Indeed, the `"="` operator is defined in both packages, and both are visible at the place it is used.  The first declaration is an implicit one, which occurs when the `std_logic_vector` type is declared and is an element to element comparison.  The second one is an explicit declared function, with the semantics of an unsigned comparison.
 
-With some analyser, the explicit declaration has priority over the implicit declaration, and this design can be analyzed without error.  However, this is not the rule given by the VHDL LRM, and since GHDL follows these rules,
+With some analysers, the explicit declaration has priority over the implicit declaration, and this design can be analyzed without error.  However, this is not the rule given by the VHDL LRM, and since GHDL follows these rules,
 it emits an error.
 
-You can force GHDL to use this rule with the *-fexplicit* option (see :ref:`GHDL_options` for further details). However it is easy to fix this error, by using a selected name:
+You can force GHDL to use this rule with the *-fexplicit* option (see ':ref:`GHDL:options`' for further details). However it is easy to fix this error, by using a selected name:
 
 .. code-block:: VHDL
 
-  library ieee;
-  use ieee.std_logic_unsigned.all;
-
-  architecture fixed_bad of counter
-  is
-     signal v : std_logic_vector (3 downto 0);
-  begin
-     process (ck, rst)
-     begin
-       if rst = '1' then
-          v <= x"0";
-       elsif rising_edge (ck) then
-          if ieee.std_logic_unsigned."=" (v, "1010") then
-             v <= x"0";
-          else
-             v <= v + 1;
-          end if;
-       end if;
-     end process;
-
-     val <= v;
-  end fixed_bad;
-
-It is better to only use the standard packages defined by IEEE, which provides the same functionalities:
+   library ieee;
+   use ieee.std_logic_unsigned.all;
+
+   architecture fixed_bad of counter
+   is
+      signal v : std_logic_vector (3 downto 0);
+   begin
+      process (ck, rst)
+      begin
+         if rst = '1' then
+            v <= x"0";
+         elsif rising_edge (ck) then
+            if ieee.std_logic_unsigned."=" (v, "1010") then
+               v <= x"0";
+            else
+               v <= v + 1;
+            end if;
+         end if;
+      end process;
+
+      val <= v;
+   end fixed_bad;
+
+It is better to only use the standard packages defined by IEEE, which provide the same functionalities:
 
 .. code-block:: VHDL
 
-  library ieee;
-  use ieee.numeric_std.all;
-
-  architecture good of counter
-  is
-     signal v : unsigned (3 downto 0);
-  begin
-     process (ck, rst)
-     begin
-       if rst = '1' then
-          v <= x"0";
-       elsif rising_edge (ck) then
-          if v = "1010" then
-             v <= x"0";
-          else
-             v <= v + 1;
-          end if;
-       end if;
-     end process;
-
-     val <= std_logic_vector (v);
-  end good;
+   library ieee;
+   use ieee.numeric_std.all;
+
+   architecture good of counter
+   is
+      signal v : unsigned (3 downto 0);
+   begin
+      process (ck, rst)
+      begin
+         if rst = '1' then
+            v <= x"0";
+         elsif rising_edge (ck) then
+            if v = "1010" then
+               v <= x"0";
+            else
+               v <= v + 1;
+            end if;
+         end if;
+      end process;
+
+      val <= std_logic_vector (v);
+   end good;
 
 .. index:: Math_Real
 
diff --git a/doc/using/QuickStartGuide.rst b/doc/using/QuickStartGuide.rst
index a1afa00b2..803fd95f0 100644
--- a/doc/using/QuickStartGuide.rst
+++ b/doc/using/QuickStartGuide.rst
@@ -9,11 +9,11 @@ In this chapter, you will learn how to use `GHDL` by working on a few examples.
 The `'Hello world'` program
 ===========================
 
-To illustrate the large purpose of `VHDL`, here is a commented `'Hello world'` program which saved in a file named :file:`hello.vhdl`:
+To illustrate the general purpose of `VHDL`, here is a commented `'Hello world'` program which is saved in a file named :file:`hello.vhdl`:
 
 .. code-block:: VHDL
 
-   --  Hello world program.
+   --  Hello world program
    use std.textio.all; -- Imports the standard textio package.
 
    --  Defines a design entity, without any ports.
@@ -48,7 +48,7 @@ To illustrate the large purpose of `VHDL`, here is a commented `'Hello world'` p
    If a GCC/LLVM variant of `GHDL` is used:
 
    * `Analysis` generates a file, :file:`hello.o`, which is the object file corresponding to your `VHDL` program.  This is not created with mcode.
-   * The elaboration step is compulsory after the analysis and prior to launching the simulation; This wil generate an executable binary named :file:`hello_world`.
+   * The elaboration step is mandatory after running the analysis and prior to launching the simulation. This wil generate an executable binary named :file:`hello_world`.
    * As a result, :option:`-r` is just a passthrough to the binary generated in the `elaboration`. Therefore, the executable can be run directly, ``./hello_world``. See :option:`-r` for more informartion.
 
 .. HINT:: :option:`-e` can be bypassed with mcode, since :option:`-r` actually elaborates the design and saves it on memory before running the simulation. But you can still use it to check for some elaboration problems.
@@ -58,38 +58,38 @@ The `heartbeat` program
 
 .. code-block:: VHDL
 
-  entity hello_world is
-    port ( clk: out std_logic; )
-  end hearbeat;
-
-  architecture behaviour of hello_world is
-  begin
-    -- Clock process definition
-    clk_process: process
-    begin
-      clk <= '0';
-      wait for clk_period/2;
-      clk <= '1';
-      wait for clk_period/2;
-    end process;
-  end behaviour;
+   entity hello_world is
+      port ( clk: out std_logic; )
+   end hearbeat;
+
+   architecture behaviour of hello_world is
+   begin
+      -- Clock process definition
+      clk_process: process
+      begin
+         clk <= '0';
+         wait for clk_period/2;
+         clk <= '1';
+         wait for clk_period/2;
+      end process;
+   end behaviour;
 
 A full adder
 ============
 
-VHDL is generally used for hardware design.  This example starts with a `full adder <https://en.wikipedia.org/wiki/Adder_(electronics)#Full_adder>`_ described in a file named :file:`adder.vhdl`:
+VHDL is generally used for hardware design. This example starts with a `full adder <https://en.wikipedia.org/wiki/Adder_(electronics)#Full_adder>`_ described in a file named :file:`adder.vhdl`:
 
 .. code-block:: VHDL
 
    entity adder is
-     -- `i0`, `i1` and the carry-in `ci` are inputs of the adder.
-     -- `s` is the sum output, `co` is the carry-out.
-     port (i0, i1 : in bit; ci : in bit; s : out bit; co : out bit);
+      -- `i0`, `i1`, and the carry-in `ci` are inputs of the adder.
+      -- `s` is the sum output, `co` is the carry-out.
+      port (i0, i1 : in bit; ci : in bit; s : out bit; co : out bit);
    end adder;
 
    architecture rtl of adder is
    begin
-      --  This full-adder architecture contains two concurrent assignment.
+      --  This full-adder architecture contains two concurrent assignments.
       --  Compute the sum.
       s <= i0 xor i1 xor ci;
       --  Compute the carry.
@@ -107,7 +107,7 @@ You can analyze this design file, ``ghdl -a adder.vhdl``, and try to execute the
    architecture behav of adder_tb is
       --  Declaration of the component that will be instantiated.
       component adder
-        port (i0, i1 : in bit; ci : in bit; s : out bit; co : out bit);
+         port (i0, i1 : in bit; ci : in bit; s : out bit; co : out bit);
       end component;
 
       --  Specifies which entity is bound with the component.
@@ -129,14 +129,14 @@ You can analyze this design file, ``ghdl -a adder.vhdl``, and try to execute the
          --  The patterns to apply.
          type pattern_array is array (natural range <>) of pattern_type;
          constant patterns : pattern_array :=
-           (('0', '0', '0', '0', '0'),
-            ('0', '0', '1', '1', '0'),
-            ('0', '1', '0', '1', '0'),
-            ('0', '1', '1', '0', '1'),
-            ('1', '0', '0', '1', '0'),
-            ('1', '0', '1', '0', '1'),
-            ('1', '1', '0', '0', '1'),
-            ('1', '1', '1', '1', '1'));
+            (('0', '0', '0', '0', '0'),
+             ('0', '0', '1', '1', '0'),
+             ('0', '1', '0', '1', '0'),
+             ('0', '1', '1', '0', '1'),
+             ('1', '0', '0', '1', '0'),
+             ('1', '0', '1', '0', '1'),
+             ('1', '1', '0', '0', '1'),
+             ('1', '1', '1', '1', '1'));
       begin
          --  Check each pattern.
          for i in patterns'range loop
@@ -190,7 +190,7 @@ Unless you are only studying VHDL, you will work with larger designs than the on
 
 * Then, we will run the ``dlx_test_behaviour`` design.  We need to analyze all the design units for the design hierarchy, in the correct order. GHDL provides an easy way to do this, by importing the sources, ``ghdl -i --workdir=work *.vhdl``.
 
-* GHDL knows all the design units of the DLX, but no one have been analyzed. Run the make option, ``ghdl -m --workdir=work dlx_test_behaviour``, which analyzes and elaborates a design. This creates many files in the :file:`work/` directory, and (GCC/LLVM only) the :file:`dlx_test_behaviour` executable in the current directory.
+* GHDL knows all the design units of the DLX, but none of them has been analyzed. Run the make option, ``ghdl -m --workdir=work dlx_test_behaviour``, which analyzes and elaborates a design. This creates many files in the :file:`work/` directory, and (GCC/LLVM only) the :file:`dlx_test_behaviour` executable in the current directory.
 
 .. HINT:: The simulation needs to have a DLX program contained in the file :file:`dlx.out`. This memory image will be loaded in the DLX memory. Just take one sample: ``cp test_loop.out dlx.out``.
 
@@ -201,7 +201,7 @@ Unless you are only studying VHDL, you will work with larger designs than the on
      dlx-behaviour.vhdl:395:11:(assertion note): TRAP instruction
       encountered, execution halted
 
-* Last, since the clock is still running, you have to manually stop the program with the :kbd:`C-c` key sequence.  This behavior prevents you from running the test bench in batch mode. However, you may force the simulator to stop when an assertion above or equal a certain severity level occurs. To do so, call run with this option instead: ``ghdl -r --workdir=work dlx_test_behaviour --assert-level=note```. With this option, the program stops just after the previous message:
+* Lastly, since the clock is still running, you have to manually stop the program with the :kbd:`C-c` key sequence.  This behavior prevents you from running the test bench in batch mode. However, you may force the simulator to stop when an assertion above or equal a certain severity level occurs. To do so, call run with this option instead: ``ghdl -r --workdir=work dlx_test_behaviour --assert-level=note```. With this option, the program stops just after the previous message:
 
   .. code-block:: shell
 
@@ -212,7 +212,7 @@ Unless you are only studying VHDL, you will work with larger designs than the on
 .. TIP:: If you want to make room on your hard drive, you can either:
 
    * Clean the design library with the GHDL command ``ghdl --clean --workdir=work``. This removes the executable and all the object files. If you want to rebuild the design at this point, just do the make command as shown above.
-   * Remove the design library with the GHDL command ``ghdl --remove --workdir=work``. This removes the executable, all the object files and the library file. If you want to rebuild the design, you have to import the sources again, and to make the design.
+   * Remove the design library with the GHDL command ``ghdl --remove --workdir=work``. This removes the executable, all the object files and the library file. If you want to rebuild the design, you have to import the sources again and make the design.
    * Remove the :file:`work/` directory: ``rm -rf work``. Only the executable is kept. If you want to rebuild the design, create the :file:`work/` directory, import the sources, and make the design.
 
-.. WARNING:: Sometimes, a design does not fully follow the VHDL standards. For example it uses the badly engineered ``std_logic_unsigned`` package. GHDL supports this VHDL dialect through some options: ``--ieee=synopsys -fexplicit``. See section ':ref:`IEEE_library_pitfalls`', for more details.
+.. WARNING:: Sometimes, a design does not fully follow the VHDL standards. For example it might use the badly engineered ``std_logic_unsigned`` package. GHDL supports this VHDL dialect through some options: ``--ieee=synopsys -fexplicit``. See section ':ref:`IEEE_library_pitfalls`', for more details.
diff --git a/doc/using/Simulation.rst b/doc/using/Simulation.rst
index 6200d82a7..5eb624262 100644
--- a/doc/using/Simulation.rst
+++ b/doc/using/Simulation.rst
@@ -15,7 +15,7 @@ standard method in VHDL to obtain the arguments or to set the exit
 status.
 
 In GHDL, it is impossible to pass parameters to your design.  A later version
-could do it through the generics interfaces of the top entity.
+could do it through the generic interfaces of the top entity.
 
 However, the GHDL runtime behaviour can be modified with some options; for
 example, it is possible to stop simulation after a certain time.
@@ -25,7 +25,7 @@ simulation completes, or ``EXIT_FAILURE`` (1) in case of error
 (assertion failure, overflow or any constraint error).
 
 Here is the list of the most useful options.  Some debugging options are
-also available, but not described here.  The :option:`--help` options lists
+also available, but not described here.  The :option:`--help` option lists
 all options available, including the debugging one.
 
 .. option:: --assert-level<=LEVEL>
@@ -43,17 +43,17 @@ all options available, including the debugging one.
   stop simulation, but the assertion violation at the ``note`` severity
   level would only display a message.
 
-  Option :option:`--assert-level=none` prevents any assertion violation to stop
+  Option :option:`--assert-level=none` prevents any assertion violation from stopping
   simulation.
 
 .. option:: --ieee-asserts<=POLICY>
 
   Select how the assertions from ``ieee`` units are
   handled. `POLICY` can be ``enable`` (the default),
-  ``disable`` which disables all assertion from ``ieee`` packages
-  and ``disable-at-0`` which disables only at start of simulation.
+  ``disable`` which disables all assertions from ``ieee`` packages
+  and ``disable-at-0`` which disables only at the start of simulation.
 
-  This option can be useful to avoid assertion message from
+  This option can be useful to avoid assertion messages from
   ``ieee.numeric_std`` (and other ``ieee`` packages).
 
 .. option:: --stop-time<=TIME>
@@ -98,17 +98,17 @@ all options available, including the debugging one.
   If the option contains a type of delay, that is ``min=``,
   ``typ=`` or ``max=``, the annotator use respectively minimum,
   typical or maximum values.  If the option does not contain a type of delay,
-  the annotator use the typical delay.
+  the annotator uses the typical delay.
 
   See section ':ref:`Backannotation`', for more details.
 
 .. option:: --vpi<=FILENAME>
 
-Load VPI module.
+  Load VPI module.
 
 .. option:: --vpi-trace<=FILE>
 
-Trace vpi calls to FILE.
+  Trace vpi calls to FILE.
 
 .. option:: --help
 
@@ -134,21 +134,21 @@ Export waveforms
      # Path format for signals in entities :
      /top/sub/clk
 
-     # Dumps every signals named reset in first level sub entities of top
+     # Dump every signal named reset in first level sub entities of top
      /top/*/reset
 
-     # Dumps every signals named reset in recursive sub entities of top
+     # Dump every signal named reset in recursive sub entities of top
      /top/**/reset
 
-     # Dump every signals of sub2 which could be anywhere in design except on
-     # top level
+     # Dump every signal of sub2 which could be anywhere in the design except
+     # on the top level
      /**/sub2/*
 
-     # Dump every signals of sub3 which must be a first level sub entity of the
+     # Dump every signal of sub3 which must be a first level sub entity of the
      # top level
      /*/sub3/*
 
-     # Dump every signals of the first level sub entities of sub3 (but not
+     # Dump every signal of the first level sub entities of sub3 (but not
      # those of sub3)
      /**/sub3/*/*
 
@@ -209,11 +209,11 @@ Export waveforms
 
 .. option:: --vcd-nodate
 
-  Do not write date in VCD file
+  Do not write date in the VCD file.
 
 .. option:: --fst<=FILENAME>
 
-  Write the waveforms into a `fst`, that can be displayed by
+  Write the waveforms into an `fst` file that can be displayed by
   `gtkwave`. The `fst` files are much smaller than VCD or
   `GHW` files, but it handles only the same signals as the VCD format.
 
@@ -239,17 +239,13 @@ Export hierarchy and references
   This may be useful to understand the structure of a complex
   design. `KIND` is optional, but if set must be one of:
 
-  * none
-    Do not display hierarchy.  Same as if the option was not present.
+  * ``none`` Do not display hierarchy.  Same as if the option was not present.
 
-  * inst
-    Display entities, architectures, instances, blocks and generates statements.
+  * ``inst`` Display entities, architectures, instances, blocks and generates statements.
 
-  * proc
-    Like ``inst`` but also display processes.
+  * ``proc`` Like ``inst`` but also display processes.
 
-  * port
-    Like ``proc`` but display ports and signals too.
+  * ``port`` Like ``proc`` but display ports and signals too.
     If `KIND` is not specified, the hierarchy is displayed with the
     ``port`` mode.
 
@@ -259,21 +255,21 @@ Export hierarchy and references
 
 .. option:: --xref-html <[options] file...>
 
-To easily navigate through your sources, you may generate cross-references. This command generates an html file for each ``file`` given in the command line, with syntax highlighting and full cross-reference: every identifier is a link to its declaration. Besides, an index of the files is created too.
+  To easily navigate through your sources, you may generate cross-references. This command generates an html file for each ``file`` given in the command line, with syntax highlighting and full cross-reference: every identifier is a link to its declaration. An index of the files is created too.
 
-The set of ``file`` are analyzed, and then, if the analysis is successful, html files are generated in the directory specified by the :option:`-o <dir>` option, or :file:`html/` directory by default.
+  The set of ``file`` are analyzed, and then, if the analysis is successful, html files are generated in the directory specified by the :option:`-o <dir>` option, or :file:`html/` directory by default.
 
-* If the option :option:`--format=html2` is specified, then the generated html files follow the HTML 2.0 standard, and colours are specified with `<FONT>` tags. However, colours are hard-coded.
+  * If the option :option:`--format=html2` is specified, then the generated html files follow the HTML 2.0 standard, and colours are specified with `<FONT>` tags. However, colours are hard-coded.
 
-* If the option :option:`--format=css` is specified, then the generated html files follow the HTML 4.0 standard, and use the CSS-1 file :file:`ghdl.css` to specify colours. This file is generated only if it does not already exist (it is never overwritten) and can be customized by the user to change colours or appearance. Refer to a generated file and its comments for more information.
+  * If the option :option:`--format=css` is specified, then the generated html files follow the HTML 4.0 standard, and use the CSS-1 file :file:`ghdl.css` to specify colours. This file is generated only if it does not already exist (it is never overwritten) and can be customized by the user to change colours or appearance. Refer to a generated file and its comments for more information.
 
 .. option:: --psl-report<=FILENAME>
 
-Write a report for PSL at the end of simulation. For each PSL cover and assert statements, the name, source location and whether it passed or failed is reported. The file is written using the JSON format, but still being human readable.
+  Write a report for PSL at the end of simulation. For each PSL cover and assert statements, the name, source location and whether it passed or failed is reported. The file is written using the JSON format, but is still human readable.
 
 .. option:: --file-to-xml
 
-Outputs an XML representation of the decorated syntax tree for the input file and its dependencies. It can be used for VHDL tooling using semantic information, like style checkers, documentation extraction, complexity estimation...
+  Outputs an XML representation of the decorated syntax tree for the input file and its dependencies. It can be used for VHDL tooling using semantic information, like style checkers, documentation extraction, complexity estimation, etc.
 
 .. WARNING::
    * The AST slightly changes from time to time (particularly when new nodes are added for new language features), so be liberal in what is allowed by your tool. Also, the XML can be quite large so consider it only during prototyping.
@@ -287,51 +283,51 @@ Debugging
 
 .. option:: --trace-signals
 
-Display signals after each cycle.
+  Display signals after each cycle.
 
 .. option:: --trace-processes
 
-Display process name before each cycle.
+  Display process name before each cycle.
 
 .. option:: --stats
 
-Display run-time statistics.
+  Display run-time statistics.
 
 .. option:: --disp-order
 
-Display signals order.
+  Display signals order.
 
 .. option:: --disp-sources
 
-Display sources while displaying signals.
+  Display sources while displaying signals.
 
 .. option:: --disp-sig-types
 
-Display signal types.
+  Display signal types.
 
 .. option:: --disp-signals-map
 
-Display map bw declared signals and internal signals.
+  Display map bw declared signals and internal signals.
 
 .. option:: --disp-signals-table
 
-Display internal signals.
+  Display internal signals.
 
 .. option:: --checks
 
-Do internal checks after each process run.
+  Do internal checks after each process run.
 
 .. option:: --activity<=LEVEL>
 
-Watch activity of LEVEL signals: LEVEL is all, min (default) or none (unsafe).
+  Watch activity of LEVEL signals: LEVEL is ``all``, ``min`` (default) or ``none`` (unsafe).
 
 .. option:: --dump-rti
 
-Dump Run Time Information (RTI).
+  Dump Run Time Information (RTI).
 
 .. option:: --bootstrap
 
-Allow ``--work=std``
+  Allow ``--work=std``
 
 GNU Debugger (GDB)
 ------------------
@@ -342,7 +338,7 @@ GNU Debugger (GDB)
 
 GDB is a general purpose debugger for programs compiled by GCC. Currently, there is no VHDL support for GDB. It may be difficult to inspect variables or signals in GDB. However, it is still able to display the stack frame in case of error or to set a breakpoint at a specified line.
 
-GDB can be useful to precisely catch a runtime error, such as indexing an array beyond its bounds. All error check subprograms call the ``__ghdl_fatal`` procedure. Therefore, to catch runtime error, set a breakpoint like this::
+GDB can be useful to catch a runtime error, such as indexing an array beyond its bounds. All error check subprograms call the ``__ghdl_fatal`` procedure. Therefore, to a catch runtime error, set a breakpoint like this::
 
   (gdb) break __ghdl_fatal