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| author | Tristan Gingold <tgingold@free.fr> | 2021-09-15 05:40:44 +0200 |
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| committer | Tristan Gingold <tgingold@free.fr> | 2021-09-15 05:40:44 +0200 |
| commit | f75191ef6e013c4efaa8b68eee93e4de47254db9 (patch) | |
| tree | 156936782a82c210abc916b4b254d75ee2edb6b6 /doc/using/Simulation.rst | |
| parent | efcf7034d651a59c7698b30cf20c1cea6458bb17 (diff) | |
| download | ghdl-f75191ef6e013c4efaa8b68eee93e4de47254db9.tar.gz ghdl-f75191ef6e013c4efaa8b68eee93e4de47254db9.tar.bz2 ghdl-f75191ef6e013c4efaa8b68eee93e4de47254db9.zip | |
synth/netlists-disp_verilog: fix output of parameter values. For #1866
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