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+\input texinfo   @c -*-texinfo-*-
+@c %**start of header
+@setfilename GHDL.info
+@documentencoding UTF-8
+@ifinfo
+@*Generated by Sphinx 1.3.1.@*
+@end ifinfo
+@settitle GHDL Documentation
+@defindex ge
+@paragraphindent 0
+@exampleindent 4
+@finalout
+@dircategory Miscellaneous
+@direntry
+* GHDL: (GHDL.info). VHDL simulator.
+@end direntry
+
+@definfoenclose strong,`,'
+@definfoenclose emph,`,'
+@c %**end of header
+
+@copying
+@quotation
+GHDL 0.33, November 24, 2015
+
+Tristan Gingold
+
+Copyright @copyright{} 2015, Tristan Gingold
+@end quotation
+
+@end copying
+
+@titlepage
+@title GHDL Documentation
+@insertcopying
+@end titlepage
+@contents
+
+@c %** start of user preamble
+
+@c %** end of user preamble
+
+@ifnottex
+@node Top
+@top GHDL Documentation
+@insertcopying
+@end ifnottex
+
+@c %**start of body
+@anchor{index doc}@anchor{0}
+@c GHDL documentation master file, created by
+@c sphinx-quickstart on Fri Nov 20 20:33:03 2015.
+@c You can adapt this file completely to your liking, but it should at least
+@c contain the root `toctree` directive.
+
+Contents:
+
+@menu
+* Introduction:: 
+* Starting with GHDL:: 
+* Invoking GHDL:: 
+* Simulation and runtime:: 
+* GHDL implementation of VHDL:: 
+* GHDL implementation of VITAL:: 
+* Flaws and bugs report:: 
+* Copyrights:: 
+* Indices and tables:: 
+* Index:: 
+
+@detailmenu
+ --- The Detailed Node Listing ---
+
+Introduction
+
+* Content of this manual:: 
+* What is VHDL?:: 
+* What is GHDL?:: 
+
+Starting with GHDL
+
+* The hello world program:: 
+* A full adder:: 
+* Starting with a design:: 
+
+Invoking GHDL
+
+* Building commands:: 
+* GHDL options:: 
+* Passing options to other programs:: 
+* GHDL warnings:: 
+* Rebuilding commands:: 
+* Library commands:: 
+* Cross-reference command:: 
+* File commands:: 
+* Misc commands:: 
+* Installation Directory:: 
+* IEEE library pitfalls:: 
+* IEEE math packages:: 
+
+Building commands
+
+* Analysis command:: 
+* Elaboration command:: 
+* Run command:: 
+* Elaborate and run command:: 
+* Bind command:: 
+* Link command:: 
+* List link command:: 
+* Check syntax command:: 
+* Analyze and elaborate command:: 
+
+Rebuilding commands
+
+* Import command:: 
+* Make command:: 
+* Generate Makefile command:: 
+
+Library commands
+
+* Directory command:: 
+* Clean command:: 
+* Remove command:: 
+* Copy command:: 
+* Create a Library:: 
+
+File commands
+
+* Pretty print command:: 
+* Find command:: 
+* Chop command:: 
+* Lines command:: 
+
+Misc commands
+
+* Help command:: 
+* Disp config command:: 
+* Disp standard command:: 
+* Version command:: 
+
+Simulation and runtime
+
+* Simulation options:: 
+* Debugging VHDL programs:: 
+
+GHDL implementation of VHDL
+
+* VHDL standards:: 
+* PSL implementation:: 
+* Source representation:: 
+* Library database:: 
+* Top entity:: 
+* Using vendor libraries:: 
+* Interfacing to other languages:: 
+
+Interfacing to other languages
+
+* Foreign declarations:: 
+* Restrictions on foreign declarations:: 
+* Linking with foreign object files:: 
+* Starting a simulation from a foreign program:: 
+* Linking with Ada:: 
+* Using GRT from Ada:: 
+
+GHDL implementation of VITAL
+
+* VITAL packages:: 
+* VHDL restrictions for VITAL:: 
+* Backannotation:: 
+* Negative constraint calculation:: 
+
+Flaws and bugs report
+
+* Reporting bugs:: 
+* Future improvements:: 
+
+@end detailmenu
+@end menu
+
+@node Introduction,Starting with GHDL,Top,Top
+@anchor{Introduction welcome-to-ghdl-s-documentation}@anchor{1}@anchor{Introduction introduction}@anchor{2}@anchor{Introduction doc}@anchor{3}
+@chapter Introduction
+
+
+@menu
+* Content of this manual:: 
+* What is VHDL?:: 
+* What is GHDL?:: 
+
+@end menu
+
+@node Content of this manual,What is VHDL?,,Introduction
+@anchor{Introduction content-of-this-manual}@anchor{4}
+@section Content of this manual
+
+
+This manual is the user and reference manual for GHDL.  It does not
+contain an introduction to VHDL.  Thus, the reader should have at least
+a basic knowledge of VHDL.  A good knowledge of VHDL language reference
+manual (usually called LRM) is a plus.
+
+@node What is VHDL?,What is GHDL?,Content of this manual,Introduction
+@anchor{Introduction what-is-vhdl}@anchor{5}
+@section What is @cite{VHDL}?
+
+
+@cite{VHDL} is an acronym for Very High Speed Integrated Circuit Hardware
+Description Language which is a programming language used to describe a
+logic circuit by function, data flow behaviour, or structure.
+
+@cite{VHDL} @emph{is} a programming language: although @cite{VHDL} was
+not designed for writing general purpose programs, you can write any
+algorithm with the @cite{VHDL} language.  If you are able to write
+programs, you will find in @cite{VHDL} features similar to those found
+in procedural languages such as @cite{C}, @cite{Python}, or @cite{Ada}.
+@cite{VHDL} derives most of its syntax and semantics from @cite{Ada}.
+Knowing @cite{Ada} is an advantage for learning @cite{VHDL} (it is an
+advantage in general as well).
+
+However, @cite{VHDL} was not designed as a general purpose language but as an
+@cite{HDL} (hardware description language).  As the name implies, @cite{VHDL}
+aims at modeling or documenting electronics systems.  Due to the nature
+of hardware components which are always running, @cite{VHDL} is a highly
+concurrent language, built upon an event-based timing model.
+
+Like a program written in any other language, a @cite{VHDL} program
+can be executed. Since @cite{VHDL} is used to model designs, the term
+@emph{simulation} is often used instead of @cite{execution}, with the
+same meaning.
+
+Like a program written in another hardware description language, a
+@cite{VHDL} program can be transformed with a @emph{synthesis tool}
+into a netlist, that is, a detailed gate-level implementation.
+
+@node What is GHDL?,,What is VHDL?,Introduction
+@anchor{Introduction what-is-ghdl}@anchor{6}
+@section What is @cite{GHDL}?
+
+
+@cite{GHDL} is a shorthand for G Hardware Design Language.  Currently,
+@cite{G} has no meaning.
+
+@cite{GHDL} is a @cite{VHDL} compiler that can execute (nearly) any
+@cite{VHDL} program. @cite{GHDL} is @emph{not} a synthesis tool: you cannot
+create a netlist with @cite{GHDL}.
+
+Unlike some other simulators, @cite{GHDL} is a compiler: it directly
+translates a @cite{VHDL} file to machine code, using the @cite{GCC} or @cite{LLVM}
+back-end and without using an intermediary language such as @cite{C}
+or @cite{C++}.  Therefore, the compiled code should be faster and
+the analysis time should be shorter than with a compiler using an
+intermediary language.
+
+The Windows(TM) version of @cite{GHDL} is not based on @cite{GCC} but on
+an internal code generator.
+
+The current version of @cite{GHDL} does not contain any graphical
+viewer: you cannot see signal waves.  You can still check with a test
+bench.  The current version can produce a @cite{VCD} file which can be
+viewed with a wave viewer, as well as @cite{ghw} files to be viewed by
+@cite{gtkwave}.
+
+@cite{GHDL} aims at implementing @cite{VHDL} as defined by IEEE 1076.
+It supports most of the 1987 standard and most features added by the
+1993 standard.
+
+@node Starting with GHDL,Invoking GHDL,Introduction,Top
+@anchor{Starting_with_GHDL doc}@anchor{7}@anchor{Starting_with_GHDL starting-with-ghdl}@anchor{8}
+@chapter Starting with GHDL
+
+
+In this chapter, you will learn how to use the GHDL compiler by
+working on two examples.
+
+@menu
+* The hello world program:: 
+* A full adder:: 
+* Starting with a design:: 
+
+@end menu
+
+@node The hello world program,A full adder,,Starting with GHDL
+@anchor{Starting_with_GHDL the-hello-world-program}@anchor{9}
+@section The hello world program
+
+
+To illustrate the large purpose of VHDL, here is a commented VHDL
+"Hello world" program.
+
+@example
+--  Hello world program.
+use std.textio.all; -- Imports the standard textio package.
+
+--  Defines a design entity, without any ports.
+entity hello_world is
+end hello_world;
+
+architecture behaviour of hello_world is
+begin
+   process
+      variable l : line;
+   begin
+      write (l, String'("Hello world!"));
+      writeline (output, l);
+      wait;
+   end process;
+end behaviour;
+@end example
+
+Suppose this program is contained in the file @code{hello.vhdl}.
+First, you have to compile the file; this is called @cite{analysis} of a design
+file in VHDL terms.
+
+@example
+$ ghdl -a hello.vhdl
+@end example
+
+This command creates or updates a file @code{work-obj93.cf}, which
+describes the library @cite{work}.  On GNU/Linux, this command generates a
+file @code{hello.o}, which is the object file corresponding to your
+VHDL program.  The object file is not created on Windows.
+
+Then, you have to build an executable file.
+
+@example
+$ ghdl -e hello_world
+@end example
+
+The @code{-e} option means @emph{elaborate}.  With this option, @cite{GHDL}
+creates code in order to elaborate a design, with the @code{hello}
+entity at the top of the hierarchy.
+
+On GNU/Linux, the result is an executable program called @code{hello}
+which can be run:
+
+@example
+$ ghdl -r hello_world
+@end example
+
+or directly:
+
+@example
+$ ./hello_world
+@end example
+
+On Windows, no file is created.  The simulation is launched using this command:
+
+@example
+> ghdl -r hello_world
+@end example
+
+The result of the simulation appears on the screen:
+
+@example
+Hello world!
+@end example
+
+@node A full adder,Starting with a design,The hello world program,Starting with GHDL
+@anchor{Starting_with_GHDL a-full-adder}@anchor{a}
+@section A full adder
+
+
+VHDL is generally used for hardware design.  This example starts with
+a full adder described in the @code{adder.vhdl} file:
+
+@example
+entity adder is
+  -- `i0`, `i1` and the carry-in `ci` are inputs of the adder.
+  -- `s` is the sum output, `co` is the carry-out.
+  port (i0, i1 : in bit; ci : in bit; s : out bit; co : out bit);
+end adder;
+
+architecture rtl of adder is
+begin
+   --  This full-adder architecture contains two concurrent assignment.
+   --  Compute the sum.
+   s <= i0 xor i1 xor ci;
+   --  Compute the carry.
+   co <= (i0 and i1) or (i0 and ci) or (i1 and ci);
+end rtl;
+@end example
+
+You can analyze this design file:
+
+@example
+$ ghdl -a adder.vhdl
+@end example
+
+You can try to execute the @cite{adder} design, but this is useless,
+since nothing externally visible will happen.  In order to
+check this full adder, a testbench has to be run.  This testbench is
+very simple, since the adder is also simple: it checks exhaustively all
+inputs.  Note that only the behaviour is tested, timing constraints are
+not checked.  The file @code{adder_tb.vhdl} contains the testbench for
+the adder:
+
+@example
+--  A testbench has no ports.
+entity adder_tb is
+end adder_tb;
+
+architecture behav of adder_tb is
+   --  Declaration of the component that will be instantiated.
+   component adder
+     port (i0, i1 : in bit; ci : in bit; s : out bit; co : out bit);
+   end component;
+
+   --  Specifies which entity is bound with the component.
+   for adder_0: adder use entity work.adder;
+   signal i0, i1, ci, s, co : bit;
+begin
+   --  Component instantiation.
+   adder_0: adder port map (i0 => i0, i1 => i1, ci => ci,
+                            s => s, co => co);
+
+   --  This process does the real job.
+   process
+      type pattern_type is record
+         --  The inputs of the adder.
+         i0, i1, ci : bit;
+         --  The expected outputs of the adder.
+         s, co : bit;
+      end record;
+      --  The patterns to apply.
+      type pattern_array is array (natural range <>) of pattern_type;
+      constant patterns : pattern_array :=
+        (('0', '0', '0', '0', '0'),
+         ('0', '0', '1', '1', '0'),
+         ('0', '1', '0', '1', '0'),
+         ('0', '1', '1', '0', '1'),
+         ('1', '0', '0', '1', '0'),
+         ('1', '0', '1', '0', '1'),
+         ('1', '1', '0', '0', '1'),
+         ('1', '1', '1', '1', '1'));
+   begin
+      --  Check each pattern.
+      for i in patterns'range loop
+         --  Set the inputs.
+         i0 <= patterns(i).i0;
+         i1 <= patterns(i).i1;
+         ci <= patterns(i).ci;
+         --  Wait for the results.
+         wait for 1 ns;
+         --  Check the outputs.
+         assert s = patterns(i).s
+            report "bad sum value" severity error;
+         assert co = patterns(i).co
+            report "bad carray out value" severity error;
+      end loop;
+      assert false report "end of test" severity note;
+      --  Wait forever; this will finish the simulation.
+      wait;
+   end process;
+end behav;
+@end example
+
+As usual, you should analyze the design:
+
+@example
+$ ghdl -a adder_tb.vhdl
+@end example
+
+And build an executable for the testbench:
+
+@example
+$ ghdl -e adder_tb
+@end example
+
+You do not need to specify which object files are required: GHDL knows them
+and automatically adds them in the executable.  Now, it is time to run the
+testbench:
+
+@example
+$ ghdl -r adder_tb
+adder_tb.vhdl:52:7:(assertion note): end of test
+@end example
+
+If your design is rather complex, you'd like to inspect signals.  Signals
+value can be dumped using the VCD file format.  The resulting file can be
+read with a wave viewer such as GTKWave.  First, you should simulate your
+design and dump a waveform file:
+
+@example
+$ ghdl -r adder_tb --vcd=adder.vcd
+@end example
+
+Then, you may now view the waves:
+
+@example
+$ gtkwave adder.vcd
+@end example
+
+See @ref{b,,Simulation options}, for more details on the @ref{c,,--vcd} option and
+other runtime options.
+
+@node Starting with a design,,A full adder,Starting with GHDL
+@anchor{Starting_with_GHDL starting-with-a-design}@anchor{d}
+@section Starting with a design
+
+
+Unless you are only studying VHDL, you will work with bigger designs than
+the ones of the previous examples.
+
+Let's see how to analyze and run a bigger design, such as the DLX model
+suite written by Peter Ashenden which is distributed under the terms of the
+GNU General Public License.  A copy is kept on
+@indicateurl{http://ghdl.free.fr/dlx.tar.gz}
+
+First, untar the sources:
+
+@example
+$ tar zxvf dlx.tar.gz
+@end example
+
+In order not to pollute the sources with the library, it is a good idea
+to create a @code{work/} subdirectory for the @cite{WORK} library.  To
+any GHDL commands, we will add the @code{--workdir=work} option, so
+that all files generated by the compiler (except the executable) will be
+placed in this directory.
+
+@example
+$ cd dlx
+$ mkdir work
+@end example
+
+We will run the @code{dlx_test_behaviour} design.  We need to analyze
+all the design units for the design hierarchy, in the correct order.
+GHDL provides an easy way to do this, by importing the sources:
+
+@example
+$ ghdl -i --workdir=work *.vhdl
+@end example
+
+and making a design:
+
+@example
+$ ghdl -m --workdir=work dlx_test_behaviour
+@end example
+
+Before this second stage, GHDL knows all the design units of the DLX,
+but no one have been analyzed.  The make command of GHDL analyzes and
+elaborates a design.  This creates many files in the @code{work/}
+directory, and the @code{dlx_test_behaviour} executable in the current
+directory.
+
+The simulation needs to have a DLX program contained in the file
+@code{dlx.out}.  This memory image will be be loaded in the DLX memory.
+Just take one sample:
+
+@example
+$ cp test_loop.out dlx.out
+@end example
+
+And you can run the test suite:
+
+@example
+$ ghdl -r dlx_test_behaviour
+@end example
+
+The test bench monitors the bus and displays each instruction executed.
+It finishes with an assertion of severity level note:
+
+@example
+dlx-behaviour.vhdl:395:11:(assertion note): TRAP instruction
+ encountered, execution halted
+@end example
+
+Since the clock is still running, you have to manually stop the program
+with the @code{C-c} key sequence.  This behavior prevents you from running the
+test bench in batch mode.  However, you may force the simulator to
+stop when an assertion above or equal a certain severity level occurs:
+
+@example
+$ ghdl -r dlx_test_behaviour --assert-level=note
+@end example
+
+With this option, the program stops just after the previous message:
+
+@example
+dlx-behaviour.vhdl:395:11:(assertion note): TRAP instruction
+ encountered, execution halted
+error: assertion failed
+@end example
+
+If you want to make room on your hard drive, you can either:
+
+
+@itemize *
+
+@item 
+clean the design library with the GHDL command:
+
+@example
+$ ghdl --clean --workdir=work
+@end example
+
+This removes the executable and all the object files.  If you want to
+rebuild the design at this point, just do the make command as shown
+above.
+
+@item 
+remove the design library with the GHDL command:
+
+@example
+$ ghdl --remove --workdir=work
+@end example
+
+This removes the executable, all the object files and the library file.
+If you want to rebuild the design, you have to import the sources again,
+and to make the design.
+
+@item 
+remove the @code{work/} directory:
+
+@example
+$ rm -rf work
+@end example
+
+Only the executable is kept.  If you want to rebuild the design, create
+the @code{work/} directory, import the sources, and make the design.
+@end itemize
+
+Sometimes, a design does not fully follow the VHDL standards.  For example it
+uses the badly engineered @code{std_logic_unsigned} package.  GHDL supports
+this VHDL dialect through some options:
+
+@example
+--ieee=synopsys -fexplicit
+@end example
+
+See @ref{e,,IEEE library pitfalls}, for more details.
+
+@node Invoking GHDL,Simulation and runtime,Starting with GHDL,Top
+@anchor{Invoking_GHDL invoking-ghdl}@anchor{f}@anchor{Invoking_GHDL doc}@anchor{10}
+@chapter Invoking GHDL
+
+
+The form of the @code{ghdl} command is:
+
+@example
+ghdl command [options...]
+@end example
+
+The GHDL program has several commands.  The first argument selects
+the command.  The options are used to slightly modify the action.
+
+No option is allowed before the command.  Except for the run command,
+no option is allowed after a filename or a unit name.
+
+@menu
+* Building commands:: 
+* GHDL options:: 
+* Passing options to other programs:: 
+* GHDL warnings:: 
+* Rebuilding commands:: 
+* Library commands:: 
+* Cross-reference command:: 
+* File commands:: 
+* Misc commands:: 
+* Installation Directory:: 
+* IEEE library pitfalls:: 
+* IEEE math packages:: 
+
+@end menu
+
+@node Building commands,GHDL options,,Invoking GHDL
+@anchor{Invoking_GHDL building-commands}@anchor{11}
+@section Building commands
+
+
+The mostly used commands of GHDL are those to analyze and elaborate a design.
+
+@menu
+* Analysis command:: 
+* Elaboration command:: 
+* Run command:: 
+* Elaborate and run command:: 
+* Bind command:: 
+* Link command:: 
+* List link command:: 
+* Check syntax command:: 
+* Analyze and elaborate command:: 
+
+@end menu
+
+@node Analysis command,Elaboration command,,Building commands
+@anchor{Invoking_GHDL analysis-command}@anchor{12}
+@subsection Analysis command
+
+
+@geindex analysis
+
+@geindex *-a* command
+
+Analyze one or severals files:
+
+@example
+ghdl -a [options...] file...
+@end example
+
+The analysis command compiles one or more files, and creates an
+object file for each source file.  The analysis command is selected with
+@code{-a} switch.  Any argument starting with a dash is an option, the
+others are filenames.  No options are allowed after a filename
+argument. GHDL analyzes each filename in the given order, and stops the
+analysis in case of error (the following files are not analyzed).
+
+See @ref{13,,GHDL options}, for details on the GHDL options.  For example,
+to produce debugging information such as line numbers, use:
+
+@example
+ghdl -a -g my_design.vhdl
+@end example
+
+@node Elaboration command,Run command,Analysis command,Building commands
+@anchor{Invoking_GHDL id1}@anchor{14}@anchor{Invoking_GHDL elaboration-command}@anchor{15}
+@subsection Elaboration command
+
+
+@geindex elaboration
+
+@geindex *-e* command
+
+Elaborate a design:
+
+@example
+ghdl -e [options..] primary_unit [secondary_unit]
+@end example
+
+On GNU/Linux the elaboration command creates an executable
+containing the code of the @cite{VHDL} sources, the elaboration code
+and simulation code to execute a design hierarchy. On Windows this
+command elaborates the design but does not generate anything.
+
+The elaboration command is selected with @code{-e} switch, and must be
+followed by either:
+
+
+@itemize *
+
+@item 
+a name of a configuration unit
+
+@item 
+a name of an entity unit
+
+@item 
+a name of an entity unit followed by a name of an architecture unit
+@end itemize
+
+Name of the units must be a simple name, without any dot.  You can
+select the name of the @cite{WORK} library with the @code{--work=NAME}
+option, as described in @ref{13,,GHDL options}.
+
+See @ref{16,,Top entity}, for the restrictions on the root design of a
+hierarchy.
+
+On GNU/Linux the filename of the executable is the name of the
+primary unit, or for the later case, the concatenation of the name of
+the primary unit, a dash, and the name of the secondary unit (or
+architecture).  On Windows there is no executable generated.
+
+The @code{-o} followed by a filename can override the default
+executable filename.
+
+For the elaboration command, @cite{GHDL} re-analyzes all the
+configurations, entities, architectures and package declarations, and
+creates the default configurations and the default binding indications
+according to the LRM rules.  It also generates the list of objects files
+required for the executable.  Then, it links all these files with the
+runtime library.
+
+The actual elaboration is performed at runtime.
+
+On Windows this command can be skipped because it is also done by the
+run command.
+
+@node Run command,Elaborate and run command,Elaboration command,Building commands
+@anchor{Invoking_GHDL run-command}@anchor{17}@anchor{Invoking_GHDL id2}@anchor{18}
+@subsection Run command
+
+
+@geindex run
+
+@geindex *-r* command
+
+Run (or simulate) a design:
+
+@example
+ghdl -r [options...] primary_unit [secondary_unit] [simulation_options...]
+@end example
+
+The options and arguments are the same as for the elaboration command, @ref{15,,Elaboration command}.
+
+On GNU/Linux this command simply determines the filename of the executable
+and executes it.  Options are ignored. You may also directly execute
+the program.
+
+This command exists for three reasons:
+
+
+@itemize *
+
+@item 
+You don't have to create the executable program name.
+
+@item 
+It is coherent with the @code{-a} and @code{-e} commands.
+
+@item 
+It works with the Windows implementation, where the code is generated in
+memory.
+@end itemize
+
+On Windows this command elaborates and launches the simulation.  As a consequence
+you must use the same options used during analysis.
+
+See @ref{19,,Simulation and runtime}, for details on options.
+
+@node Elaborate and run command,Bind command,Run command,Building commands
+@anchor{Invoking_GHDL elaborate-and-run-command}@anchor{1a}
+@subsection Elaborate and run command
+
+
+@geindex elaborate and run
+
+@geindex *--elab-run* command
+
+Elaborate and then simulate a design unit:
+
+@example
+ghdl --elab-run [elab_options...] primary_unit [secondary_unit] [run_options...]
+@end example
+
+This command acts like the elaboration command (see @ref{15,,Elaboration command})
+followed by the run command (see @ref{17,,Run command}).
+
+@node Bind command,Link command,Elaborate and run command,Building commands
+@anchor{Invoking_GHDL bind-command}@anchor{1b}@anchor{Invoking_GHDL id3}@anchor{1c}
+@subsection Bind command
+
+
+@geindex binding
+
+@geindex *--bind* command
+
+Bind a design unit and prepare the link step:
+
+@example
+ghdl --bind [options] primary_unit [secondary_unit]
+@end example
+
+This command is only available on GNU/Linux.
+
+This performs only the first stage of the elaboration command; the list
+of objects files is created but the executable is not built.  This
+command should be used only when the main entry point is not ghdl.
+
+@node Link command,List link command,Bind command,Building commands
+@anchor{Invoking_GHDL link-command}@anchor{1d}@anchor{Invoking_GHDL id4}@anchor{1e}
+@subsection Link command
+
+
+@geindex linking
+
+@geindex *--link* command
+
+Link an already bound design unit:
+
+@example
+ghdl --link [options] primary_unit [secondary_unit]
+@end example
+
+This performs only the second stage of the elaboration command: the
+executable is created by linking the files of the object files list.
+This command is available only for completeness.  The elaboration command is
+equivalent to the bind command followed by the link command.
+
+@node List link command,Check syntax command,Link command,Building commands
+@anchor{Invoking_GHDL list-link-command}@anchor{1f}@anchor{Invoking_GHDL id5}@anchor{20}
+@subsection List link command
+
+
+@geindex *--list-link* command
+
+Display files which will be linked:
+
+@example
+ghdl --list-link primary_unit [secondary_unit]
+@end example
+
+This command is only available on GNU/Linux.
+
+This command may be used only after a bind command.  GHDL displays all
+the files which will be linked to create an executable.  This command is
+intended to add object files in a link of a foreign program.
+
+@node Check syntax command,Analyze and elaborate command,List link command,Building commands
+@anchor{Invoking_GHDL id6}@anchor{21}@anchor{Invoking_GHDL check-syntax-command}@anchor{22}
+@subsection Check syntax command
+
+
+@geindex checking syntax
+
+@geindex *-s* command
+
+Analyze files but do not generate code:
+
+@example
+ghdl -s [options] files
+@end example
+
+This command may be used to check the syntax of files.  It does not update
+the library.
+
+@node Analyze and elaborate command,,Check syntax command,Building commands
+@anchor{Invoking_GHDL analyze-and-elaborate-command}@anchor{23}@anchor{Invoking_GHDL id7}@anchor{24}
+@subsection Analyze and elaborate command
+
+
+@geindex Analyze and elaborate command
+
+@geindex *-c* command
+
+Analyze files and elaborate them at the same time.
+
+On GNU/Linux:
+
+@example
+ghdl -c [options] file... -e primary_unit [secondary_unit]
+@end example
+
+On Windows:
+
+@example
+ghdl -c [options] file... -r primary_unit [secondary_unit]
+@end example
+
+This command combines analysis and elaboration: files are analyzed and
+the unit is then elaborated.  However, code is only generated during the
+elaboration.  On Windows the simulation is launched.
+
+To be more precise, the files are first parsed, and then the elaboration
+drives the analysis.  Therefore, there is no analysis order, and you don't
+need to care about it.
+
+All the units of the files are put into the @cite{work} library.  But, the
+work library is neither read from disk nor saved.  Therefore, you must give
+all the files of the @cite{work} library your design needs.
+
+The advantages over the traditional approach (analyze and then elaborate) are:
+
+
+@itemize *
+
+@item 
+The compilation cycle is achieved in one command.
+
+@item 
+Since the files are only parsed once, the compilation cycle may be faster.
+
+@item 
+You don't need to know an analysis order
+
+@item 
+This command produces smaller executable, since unused units and subprograms
+do not generate code.
+@end itemize
+
+However, you should know that currently most of the time is spent in code
+generation and the analyze and elaborate command generate code for all units
+needed, even units of @code{std} and @code{ieee} libraries.  Therefore,
+according to the design, the time for this command may be higher than the time
+for the analyze command followed by the elaborate command.
+
+This command is still experimental.  In case of problems, you should go back
+to the traditional way.
+
+@node GHDL options,Passing options to other programs,Building commands,Invoking GHDL
+@anchor{Invoking_GHDL ghdl-options}@anchor{13}@anchor{Invoking_GHDL id8}@anchor{25}
+@section GHDL options
+
+
+@geindex IEEE 1164
+
+@geindex 1164
+
+@geindex IEEE 1076.3
+
+@geindex 1076.3
+
+Besides the options described below, @cite{GHDL} passes any debugging options
+(those that begin with @code{-g}) and optimizations options (those that
+begin with @code{-O} or @code{-f}) to @cite{GCC}.  Refer to the @cite{GCC}
+manual for details.
+
+@c option::--work=<NAME>
+@c 
+@c .. index:: WORK library
+@c 
+@c Specify the name of the :samp:`WORK` library.  Analyzed units are always
+@c placed in the library logically named :samp:`WORK`.  With this option,
+@c you can set its name.  By default, the name is :samp:`work`.
+@c 
+@c `GHDL` checks whether :samp:`WORK` is a valid identifier.  Although being
+@c more or less supported, the :samp:`WORK` identifier should not be an
+@c extended identifier, since the filesystem may prevent it from correctly
+@c working (due to case sensitivity or forbidden characters in filenames).
+@c 
+@c `VHDL` rules forbid you to add units to the :samp:`std` library.
+@c Furthermore, you should not put units in the :samp:`ieee` library.
+
+@geindex command line option; --workdir=<DIR>
+@anchor{Invoking_GHDL cmdoption--workdir}@anchor{26}
+@deffn {Option} @w{-}@w{-}workdir=<DIR>
+
+Specify the directory where the @code{WORK} library is located.  When this
+option is not present, the @code{WORK} library is in the current
+directory.  The object files created by the compiler are always placed
+in the same directory as the @code{WORK} library.
+
+Use option @ref{27,,-P} to specify where libraries other than @code{WORK}
+are placed.
+@end deffn
+
+@geindex command line option; --std=<STD>
+@anchor{Invoking_GHDL cmdoption--std}@anchor{28}
+@deffn {Option} @w{-}@w{-}std=<STD>
+
+Specify the standard to use.  By default, the standard is @code{93c}, which
+means VHDL-93 accepting VHDL-87 syntax.  For details on @code{STD} values see
+@ref{29,,VHDL standards}.
+@end deffn
+
+@geindex command line option; --ieee=<VER>
+@anchor{Invoking_GHDL cmdoption--ieee}@anchor{2a}
+@deffn {Option} @w{-}@w{-}ieee=<VER>
+
+@geindex ieee library
+
+@geindex synopsys library
+
+@geindex mentor library
+
+Select the @code{IEEE} library to use. @code{VER} must be one of:
+
+
+@table @asis
+
+@item none
+
+Do not supply an @cite{IEEE} library.  Any library clause with the @code{IEEE}
+identifier will fail, unless you have created by your own a library with
+the @cite{IEEE} name.
+
+@item standard
+
+Supply an @cite{IEEE} library containing only packages defined by
+@code{ieee} standards.  Currently, there are the multivalue logic system
+packages @code{std_logic_1164} defined by IEEE 1164, the synthesis
+packages , @code{numeric_bit} and @code{numeric_std} defined by IEEE
+1076.3, and the @code{vital} packages @code{vital_timing} and
+@code{vital_primitives}, defined by IEEE 1076.4.  The version of these
+packages is defined by the VHDL standard used.  See @ref{2b,,VITAL packages},
+for more details.
+
+@item synopsys
+
+Supply the former packages and the following additional packages:
+@code{std_logic_arith}, @code{std_logic_signed},
+@code{std_logic_unsigned}, @code{std_logic_textio}.
+
+These packages were created by some companies, and are popular.  However
+they are not standard packages, and have been placed in the @cite{IEEE}
+library without the permission from the @code{ieee}.
+
+@item mentor
+
+Supply the standard packages and the following additional package:
+@code{std_logic_arith}.  The package is a slight variation of a definitely
+not standard but widely mis-used package.
+@end table
+
+To avoid errors, you must use the same @cite{IEEE} library for all units of
+your design, and during elaboration.
+@end deffn
+
+@geindex command line option; -P<DIRECTORY>
+@anchor{Invoking_GHDL cmdoption-P}@anchor{27}
+@deffn {Option} @w{-}P<DIRECTORY>
+
+Add @cite{DIRECTORY} to the end of the list of directories to be searched for
+library files.
+
+The @cite{WORK} library is always searched in the path specified by the
+@code{--workdir=} option, or in the current directory if the latter
+option is not specified.
+@end deffn
+
+@geindex command line option; -fexplicit
+@anchor{Invoking_GHDL cmdoption-fexplicit}@anchor{2c}
+@deffn {Option} @w{-}fexplicit
+
+When two operators are overloaded, give preference to the explicit declaration.
+This may be used to avoid the most common pitfall of the @code{std_logic_arith}
+package.  See @ref{e,,IEEE library pitfalls}, for an example.
+
+This option is not set by default.  I don't think this option is a
+good feature, because it breaks the encapsulation rule.  When set, an
+operator can be silently overridden in another package.  You'd better to fix
+your design and use the @code{numeric_std} package.
+@end deffn
+
+@geindex command line option; -frelaxed-rules
+@anchor{Invoking_GHDL cmdoption-frelaxed-rules}@anchor{2d}
+@deffn {Option} @w{-}frelaxed@w{-}rules
+
+Within an object declaration, allow to reference the name (which
+references the hidden declaration).  This ignores the error in the
+following code:
+
+@example
+package pkg1 is
+ type state is (state1, state2, state3);
+end pkg1;
+
+use work.pkg1.all;
+package pkg2 is
+ constant state1 : state := state1;
+end pkg2;
+@end example
+
+Some code (such as Xilinx packages) have such constructs, which
+are valid.
+
+(The scope of the @code{state1} constant start at the @cite{constant}
+word. Because the constant @code{state1} and the enumeration literal
+@code{state1} are homograph, the enumeration literal is hidden in the
+immediate scope of the constant).
+@end deffn
+
+@geindex command line option; -fpsl
+@anchor{Invoking_GHDL cmdoption-fpsl}@anchor{2e}
+@deffn {Option} @w{-}fpsl
+
+Enable parsing of PSL assertions within comments.  See @ref{2f,,PSL implementation},
+for more details.
+@end deffn
+
+@geindex command line option; --no-vital-checks
+@anchor{Invoking_GHDL cmdoption--no-vital-checks}@anchor{30}
+@deffn {Option} @w{-}@w{-}no@w{-}vital@w{-}checks
+@end deffn
+
+@geindex command line option; --vital-checks
+@anchor{Invoking_GHDL cmdoption--vital-checks}@anchor{31}
+@deffn {Option} @w{-}@w{-}vital@w{-}checks
+
+Disable or enable checks of restriction on VITAL units.  Checks are enabled
+by default.
+
+Checks are performed only when a design unit is decorated by a VITAL attribute.
+The VITAL attributes are @code{VITAL_Level0} and @code{VITAL_Level1}, both
+declared in the @code{ieee.VITAL_Timing} package.
+
+Currently, VITAL checks are only partially implemented.  See
+@ref{32,,VHDL restrictions for VITAL}, for more details.
+@end deffn
+
+@geindex command line option; --syn-binding
+@anchor{Invoking_GHDL cmdoption--syn-binding}@anchor{33}
+@deffn {Option} @w{-}@w{-}syn@w{-}binding
+
+Use synthesizer rules for component binding.  During elaboration, if a
+component is not bound to an entity using VHDL LRM rules, try to find
+in any known library an entity whose name is the same as the component
+name.
+
+This rule is known as synthesizer rule.
+
+There are two key points: normal VHDL LRM rules are tried first and
+entities are searched only in known library.  A known library is a
+library which has been named in your design.
+
+This option is only useful during elaboration.
+@end deffn
+
+@geindex command line option; --PREFIX=<PATH>
+@anchor{Invoking_GHDL cmdoption--PREFIX}@anchor{34}
+@deffn {Option} @w{-}@w{-}PREFIX=<PATH>
+
+Use @code{PATH} as the prefix path to find commands and pre-installed (std and
+ieee) libraries.
+@end deffn
+
+@geindex command line option; --GHDL1=<COMMAND>
+@anchor{Invoking_GHDL cmdoption--GHDL1}@anchor{35}
+@deffn {Option} @w{-}@w{-}GHDL1=<COMMAND>
+
+Use @code{COMMAND} as the command name for the compiler.  If @code{COMMAND} is
+not a path, then it is search in the list of program directories.
+@end deffn
+
+@geindex command line option; -v
+@anchor{Invoking_GHDL cmdoption-v}@anchor{36}
+@deffn {Option} @w{-}v
+
+Be verbose.  For example, for analysis, elaboration and make commands, GHDL
+displays the commands executed.
+@end deffn
+
+@node Passing options to other programs,GHDL warnings,GHDL options,Invoking GHDL
+@anchor{Invoking_GHDL passing-options-to-other-programs}@anchor{37}
+@section Passing options to other programs
+
+
+These options are only available on GNU/Linux.
+
+For many commands, @cite{GHDL} acts as a driver: it invokes programs to perform
+the command.  You can pass arbitrary options to these programs.
+
+Both the compiler and the linker are in fact GCC programs.  See the
+GCC manual for details on GCC options.
+
+@geindex command line option; -Wc@comma{}<OPTION>
+@anchor{Invoking_GHDL cmdoption-Wc}@anchor{38}
+@deffn {Option} @w{-}Wc,<OPTION>
+
+Pass @cite{OPTION} as an option to the compiler.
+@end deffn
+
+@geindex command line option; -Wa@comma{}<OPTION>
+@anchor{Invoking_GHDL cmdoption-Wa}@anchor{39}
+@deffn {Option} @w{-}Wa,<OPTION>
+
+Pass @cite{OPTION} as an option to the assembler.
+@end deffn
+
+@geindex command line option; -Wl@comma{}<OPTION>
+@anchor{Invoking_GHDL cmdoption-Wl}@anchor{3a}
+@deffn {Option} @w{-}Wl,<OPTION>
+
+Pass @cite{OPTION} as an option to the linker.
+@end deffn
+
+@node GHDL warnings,Rebuilding commands,Passing options to other programs,Invoking GHDL
+@anchor{Invoking_GHDL ghdl-warnings}@anchor{3b}
+@section GHDL warnings
+
+
+Some constructions are not erroneous but dubious.  Warnings are diagnostic
+messages that report such constructions.  Some warnings are reported only
+during analysis, others during elaboration.
+
+You could disable a warning by using the @code{--warn-no-XXX}
+instead of @code{--warn-XXX}.
+
+@geindex command line option; --warn-reserved
+@anchor{Invoking_GHDL cmdoption--warn-reserved}@anchor{3c}
+@deffn {Option} @w{-}@w{-}warn@w{-}reserved
+
+Emit a warning if an identifier is a reserved word in a later VHDL standard.
+@end deffn
+
+@geindex command line option; --warn-default-binding
+@anchor{Invoking_GHDL cmdoption--warn-default-binding}@anchor{3d}
+@deffn {Option} @w{-}@w{-}warn@w{-}default@w{-}binding
+
+During analyze, warns if a component instantiation has neither
+configuration specification nor default binding.  This may be useful if you
+want to detect during analyze possibly unbound component if you don't use
+configuration.  @ref{29,,VHDL standards}, for more details about default binding
+rules.
+@end deffn
+
+@geindex command line option; --warn-binding
+@anchor{Invoking_GHDL cmdoption--warn-binding}@anchor{3e}
+@deffn {Option} @w{-}@w{-}warn@w{-}binding
+
+During elaboration, warns if a component instantiation is not bound
+(and not explicitly left unbound).  Also warns if a port of an entity
+is not bound in a configuration specification or in a component
+configuration.  This warning is enabled by default, since default
+binding rules are somewhat complex and an unbound component is most
+often unexpected.
+
+However, warnings are even emitted if a component instantiation is
+inside a generate statement.  As a consequence, if you use the conditional
+generate statement to select a component according to the implementation,
+you will certainly get warnings.
+@end deffn
+
+@geindex command line option; --warn-library
+@anchor{Invoking_GHDL cmdoption--warn-library}@anchor{3f}
+@deffn {Option} @w{-}@w{-}warn@w{-}library
+
+Warns if a design unit replaces another design unit with the same name.
+@end deffn
+
+@geindex command line option; --warn-vital-generic
+@anchor{Invoking_GHDL cmdoption--warn-vital-generic}@anchor{40}
+@deffn {Option} @w{-}@w{-}warn@w{-}vital@w{-}generic
+
+Warns if a generic name of a vital entity is not a vital generic name.  This
+is set by default.
+@end deffn
+
+@geindex command line option; --warn-delayed-checks
+@anchor{Invoking_GHDL cmdoption--warn-delayed-checks}@anchor{41}
+@deffn {Option} @w{-}@w{-}warn@w{-}delayed@w{-}checks
+
+Warns for checks that cannot be done during analysis time and are
+postponed to elaboration time.  This is because not all procedure
+bodies are available during analysis (either because a package body
+has not yet been analysed or because @cite{GHDL} doesn't read not required
+package bodies).
+
+These are checks for no wait statement in a procedure called in a
+sensitized process and checks for pure rules of a function.
+@end deffn
+
+@geindex command line option; --warn-body
+@anchor{Invoking_GHDL cmdoption--warn-body}@anchor{42}
+@deffn {Option} @w{-}@w{-}warn@w{-}body
+
+Emit a warning if a package body which is not required is analyzed.  If a
+package does not declare a subprogram or a deferred constant, the package
+does not require a body.
+@end deffn
+
+@geindex command line option; --warn-specs
+@anchor{Invoking_GHDL cmdoption--warn-specs}@anchor{43}
+@deffn {Option} @w{-}@w{-}warn@w{-}specs
+
+Emit a warning if an all or others specification does not apply.
+@end deffn
+
+@geindex command line option; --warn-unused
+@anchor{Invoking_GHDL cmdoption--warn-unused}@anchor{44}
+@deffn {Option} @w{-}@w{-}warn@w{-}unused
+
+Emit a warning when a subprogram is never used.
+@end deffn
+
+@geindex command line option; --warn-error
+@anchor{Invoking_GHDL cmdoption--warn-error}@anchor{45}
+@deffn {Option} @w{-}@w{-}warn@w{-}error
+
+When this option is set, warnings are considered as errors.
+@end deffn
+
+@node Rebuilding commands,Library commands,GHDL warnings,Invoking GHDL
+@anchor{Invoking_GHDL rebuilding-commands}@anchor{46}
+@section Rebuilding commands
+
+
+Analyzing and elaborating a design consisting in several files can be tricky,
+due to dependencies.  GHDL has a few commands to rebuild a design.
+
+@menu
+* Import command:: 
+* Make command:: 
+* Generate Makefile command:: 
+
+@end menu
+
+@node Import command,Make command,,Rebuilding commands
+@anchor{Invoking_GHDL import-command}@anchor{47}
+@subsection Import command
+
+
+@geindex importing files
+
+@geindex *-i* command
+
+Add files in the work design library:
+
+@example
+ghdl -i [options] file...
+@end example
+
+All the files specified in the command line are scanned, parsed and added in
+the libraries but as not yet analyzed.  No object files are created.
+
+The purpose of this command is to localize design units in the design files.
+The make command will then be able to recursively build a hierarchy from
+an entity name or a configuration name.
+
+Since the files are parsed, there must be correct files.  However, since they
+are not analyzed, many errors are tolerated by this command.
+
+Note that all the files are added to the work library.  If you have many
+libraries, you must use the command for each library.
+
+See @ref{48,,Make command}, to actually build the design.
+
+@node Make command,Generate Makefile command,Import command,Rebuilding commands
+@anchor{Invoking_GHDL make-command}@anchor{48}@anchor{Invoking_GHDL id9}@anchor{49}
+@subsection Make command
+
+
+@geindex make
+
+@geindex *-m* command
+
+Analyze automatically outdated files and elaborate a design:
+
+@example
+ghdl -m [options] primary [secondary]
+@end example
+
+The primary unit denoted by the @code{primary} argument must already be
+known by the system, either because you have already analyzed it (even
+if you have modified it) or because you have imported it.  GHDL analyzes
+all outdated files.  A file may be outdated because it has been modified
+(e.g. you just have edited it), or because a design unit contained in
+the file depends on a unit which is outdated.  This rule is of course
+recursive.
+
+With the @code{-f} (force) option, GHDL analyzes all the units of the
+work library needed to create the design hierarchy.  Not outdated units
+are recompiled.  This is useful if you want to compile a design hierarchy
+with new compilation flags (for example, to add the @emph{-g}
+debugging option).
+
+The make command will only re-analyze design units in the work library.
+GHDL fails if it has to analyze an outdated unit from another library.
+
+The purpose of this command is to be able to compile a design without prior
+knowledge of file order.  In the VHDL model, some units must be analyzed
+before others (e.g. an entity before its architecture).  It might be a
+nightmare to analyze a full design of several files, if you don't have
+the ordered list of file.  This command computes an analysis order.
+
+The make command fails when a unit was not previously parsed.  For
+example, if you split a file containing several design units into
+several files, you must either import these new files or analyze them so
+that GHDL knows in which file these units are.
+
+The make command imports files which have been modified.  Then, a design
+hierarchy is internally built as if no units are outdated.  Then, all outdated
+design units, using the dependencies of the design hierarchy, are analyzed.
+If necessary, the design hierarchy is elaborated.
+
+This is not perfect, since the default architecture (the most recently
+analyzed one) may change while outdated design files are analyzed. In
+such a case, re-run the make command of GHDL.
+
+@node Generate Makefile command,,Make command,Rebuilding commands
+@anchor{Invoking_GHDL generate-makefile-command}@anchor{4a}
+@subsection Generate Makefile command
+
+
+@geindex *--gen-makefile* command
+
+Generate a Makefile to build a design unit:
+
+@example
+ghdl --gen-makefile [options] primary [secondary]
+@end example
+
+This command works like the make command (see @ref{48,,Make command}), but only a
+makefile is generated on the standard output.
+
+@node Library commands,Cross-reference command,Rebuilding commands,Invoking GHDL
+@anchor{Invoking_GHDL library-commands}@anchor{4b}
+@section Library commands
+
+
+GHDL has a few commands which act on a library.
+
+@menu
+* Directory command:: 
+* Clean command:: 
+* Remove command:: 
+* Copy command:: 
+* Create a Library:: 
+
+@end menu
+
+@node Directory command,Clean command,,Library commands
+@anchor{Invoking_GHDL directory-command}@anchor{4c}
+@subsection Directory command
+
+
+@geindex displaying library
+
+@geindex *-d* command
+
+Display the name of the units contained in a design library:
+
+@example
+ghdl -d [options]
+@end example
+
+The directory command, selected with the @cite{-d} command line argument
+displays the content of the work design library.  All options are
+allowed, but only a few are meaningful: @code{--work=NAME},
+@code{--workdir=PATH} and @code{--std=VER}.
+
+@node Clean command,Remove command,Directory command,Library commands
+@anchor{Invoking_GHDL clean-command}@anchor{4d}
+@subsection Clean command
+
+
+@geindex cleaning
+
+@geindex *--clean* command
+
+Remove object and executable files but keep the library:
+
+@example
+ghdl --clean [options]
+@end example
+
+GHDL tries to remove any object, executable or temporary file it could
+have created.  Source files are not removed.
+
+There is no short command line form for this option to prevent accidental
+clean up.
+
+@node Remove command,Copy command,Clean command,Library commands
+@anchor{Invoking_GHDL id10}@anchor{4e}@anchor{Invoking_GHDL remove-command}@anchor{4f}
+@subsection Remove command
+
+
+@geindex cleaning all
+
+@geindex *--remove* command
+
+Do like the clean command but remove the library too:
+
+@example
+ghdl --remove [options]
+@end example
+
+There is no short command line form for this option to prevent accidental
+clean up.  Note that after removing a design library, the files are not
+known anymore by GHDL.
+
+@node Copy command,Create a Library,Remove command,Library commands
+@anchor{Invoking_GHDL id11}@anchor{50}@anchor{Invoking_GHDL copy-command}@anchor{51}
+@subsection Copy command
+
+
+@geindex copying library
+
+@geindex *--copy* command
+
+Make a local copy of an existing library:
+
+@example
+ghdl --copy --work=name [options]
+@end example
+
+Make a local copy of an existing library.  This is very useful if you want to
+add unit to the @code{ieee} library:
+
+@example
+ghdl --copy --work=ieee --ieee=synopsys
+ghdl -a --work=ieee numeric_unsigned.vhd
+@end example
+
+@node Create a Library,,Copy command,Library commands
+@anchor{Invoking_GHDL id12}@anchor{52}@anchor{Invoking_GHDL create-a-library}@anchor{53}
+@subsection Create a Library
+
+
+@geindex create your own library
+
+A new library is created by compiling entities (packages etc.) into it:
+
+@example
+ghdl -a --work=my_custom_lib my_file.vhd
+@end example
+
+A library's source code is usually stored and compiled into its own directory,
+that you specify with the @ref{26,,--workdir} option:
+
+@example
+ghdl -a --work=my_custom_lib --workdir=my_custom_libdir my_custom_lib_srcdir/my_file.vhd
+@end example
+
+See also the @code{-PPATH} command line option.
+
+@node Cross-reference command,File commands,Library commands,Invoking GHDL
+@anchor{Invoking_GHDL id13}@anchor{54}@anchor{Invoking_GHDL cross-reference-command}@anchor{55}
+@section Cross-reference command
+
+
+To easily navigate through your sources, you may generate cross-references:
+
+@example
+ghdl --xref-html [options] file...
+@end example
+
+This command generates an html file for each @code{file} given in the command
+line, with syntax highlighting and full cross-reference: every identifier is
+a link to its declaration.  Besides, an index of the files is created too.
+
+The set of @code{file}  are analyzed, and then, if the analysis is
+successful, html files are generated in the directory specified by the
+@code{-o dir} option, or @code{html/} directory by default.
+
+If the option @code{--format=html2} is specified, then the generated html
+files follow the HTML 2.0 standard, and colours are specified with
+@cite{<FONT>} tags.  However, colours are hard-coded.
+
+If the option @code{--format=css} is specified, then the generated html files
+follow the HTML 4.0 standard, and use the CSS-1 file @code{ghdl.css} to
+specify colours.  This file is generated only if it does not already exist (it
+is never overwritten) and can be customized by the user to change colours or
+appearance.  Refer to a generated file and its comments for more information.
+
+@node File commands,Misc commands,Cross-reference command,Invoking GHDL
+@anchor{Invoking_GHDL file-commands}@anchor{56}
+@section File commands
+
+
+The following commands act on one or several files.  They do not analyze
+files, therefore, they work even if a file has semantic errors.
+
+@menu
+* Pretty print command:: 
+* Find command:: 
+* Chop command:: 
+* Lines command:: 
+
+@end menu
+
+@node Pretty print command,Find command,,File commands
+@anchor{Invoking_GHDL pretty-print-command}@anchor{57}
+@subsection Pretty print command
+
+
+@geindex *--pp-html* command
+
+@geindex pretty printing
+
+@geindex vhdl to html
+
+Generate HTML on standard output from VHDL:
+
+@example
+ghdl --pp-html [options] file...
+@end example
+
+The files are just scanned and an html file, with syntax highlighting is
+generated on standard output.
+
+Since the files are not even parsed, erroneous files or incomplete designs
+can be pretty printed.
+
+The style of the html file can be modified with the @code{--format=} option.
+By default or when the @code{--format=html2} option is specified, the output
+is an HTML 2.0 file, with colours set through @cite{<FONT>} tags.  When the
+@code{--format=css} option is specified, the output is an HTML 4.0 file,
+with colours set through a CSS file, whose name is @code{ghdl.css}.
+See @ref{55,,Cross-reference command}, for more details about this CSS file.
+
+@node Find command,Chop command,Pretty print command,File commands
+@anchor{Invoking_GHDL find-command}@anchor{58}
+@subsection Find command
+
+
+@geindex *-f* command
+
+Display the name of the design units in files:
+
+@example
+ghdl -f file...
+@end example
+
+The files are scanned, parsed and the names of design units are displayed.
+Design units marked with two stars are candidate to be at the apex of a
+design hierarchy.
+
+@node Chop command,Lines command,Find command,File commands
+@anchor{Invoking_GHDL chop-command}@anchor{59}
+@subsection Chop command
+
+
+@geindex *--chop* command
+
+Chop (or split) files at design unit:
+
+@example
+ghdl --chop files
+@end example
+
+@cite{GHDL} reads files, and writes a file in the current directory for
+every design unit.
+
+The filename of a design unit is build according to the unit.  For an
+entity declaration, a package declaration or a configuration the file
+name is @code{NAME.vhdl}, where @cite{NAME} is the name of the design
+unit.  For a package body, the filename is @code{NAME-body.vhdl}.
+Finally, for an architecture @cite{ARCH} of an entity @cite{ENTITY}, the
+filename is @code{ENTITY-ARCH.vhdl}.
+
+Since the input files are parsed, this command aborts in case of syntax
+error.  The command aborts too if a file to be written already exists.
+
+Comments between design units are stored into the most adequate files.
+
+This command may be useful to split big files, if your computer has not
+enough memory to compile such files.  The size of the executable is
+reduced too.
+
+@node Lines command,,Chop command,File commands
+@anchor{Invoking_GHDL lines-command}@anchor{5a}
+@subsection Lines command
+
+
+@geindex *--lines* command
+
+Display on the standard output lines of files preceded by line number:
+
+@example
+ghdl --lines files
+@end example
+
+@node Misc commands,Installation Directory,File commands,Invoking GHDL
+@anchor{Invoking_GHDL misc-commands}@anchor{5b}
+@section Misc commands
+
+
+There are a few GHDL commands which are seldom useful.
+
+@menu
+* Help command:: 
+* Disp config command:: 
+* Disp standard command:: 
+* Version command:: 
+
+@end menu
+
+@node Help command,Disp config command,,Misc commands
+@anchor{Invoking_GHDL id14}@anchor{5c}@anchor{Invoking_GHDL help-command}@anchor{5d}
+@subsection Help command
+
+
+@geindex *-h* command
+
+@geindex *--help* command
+
+Display (on the standard output) a short description of the all the commands
+available.  If the help switch is followed by a command switch, then options
+for this later command are displayed:
+
+@example
+ghdl --help
+ghdl -h
+ghdl -h command
+@end example
+
+@node Disp config command,Disp standard command,Help command,Misc commands
+@anchor{Invoking_GHDL disp-config-command}@anchor{5e}@anchor{Invoking_GHDL id15}@anchor{5f}
+@subsection Disp config command
+
+
+@geindex *--disp-config* command
+
+@geindex display configuration
+
+Display the program paths and options used by GHDL:
+
+@example
+ghdl --disp-config [options]
+@end example
+
+This may be useful to track installation errors.
+
+@node Disp standard command,Version command,Disp config command,Misc commands
+@anchor{Invoking_GHDL disp-standard-command}@anchor{60}
+@subsection Disp standard command
+
+
+@geindex *--disp-standard* command
+
+@geindex display ;samp;`std.standard`
+
+Display the @code{std.standard} package:
+
+@example
+ghdl --disp-standard [options]
+@end example
+
+@node Version command,,Disp standard command,Misc commands
+@anchor{Invoking_GHDL version-command}@anchor{61}
+@subsection Version command
+
+
+@geindex *--version* command
+
+@geindex version
+
+Display the @cite{GHDL} version and exit:
+
+@example
+ghdl --version
+@end example
+
+@node Installation Directory,IEEE library pitfalls,Misc commands,Invoking GHDL
+@anchor{Invoking_GHDL installation-directory}@anchor{62}
+@section Installation Directory
+
+
+During analysis and elaboration @cite{GHDL} may read the @cite{std}
+and @cite{ieee} files.  The location of these files is based on the prefix,
+which is (in priority order):
+
+
+@itemize *
+
+@item 
+the @code{--PREFIX=} command line option
+
+@item 
+the 
+@geindex GHDL_PREFIX
+@geindex environment variable; GHDL_PREFIX
+@code{GHDL_PREFIX} environment variable
+
+@item 
+a built-in default path.  It is a hard-coded path on GNU/Linux and the
+value of the @code{HKLMSoftwareGhdlInstall_Dir} registry entry on Windows.
+@end itemize
+
+You should use the @code{--disp-config} command (@ref{5e,,Disp config command} for details) to disp and debug installation problems.
+
+@node IEEE library pitfalls,IEEE math packages,Installation Directory,Invoking GHDL
+@anchor{Invoking_GHDL ieee-library-pitfalls}@anchor{e}@anchor{Invoking_GHDL id16}@anchor{63}
+@section IEEE library pitfalls
+
+
+When you use options @code{--ieee=synopsys} or @code{--ieee=mentor},
+the @cite{IEEE} library contains non standard packages such as
+@code{std_logic_arith}.
+
+These packages are not standard because there are not described by an IEEE
+standard, even if they have been put in the @cite{IEEE} library.  Furthermore,
+they are not really de-facto standard, because there are slight differences
+between the packages of Mentor and those of Synopsys.
+
+Furthermore, since they are not well-thought, their use has pitfalls.  For
+example, this description has error during compilation:
+
+@example
+library ieee;
+use ieee.std_logic_1164.all;
+
+--  A counter from 0 to 10.
+entity counter is
+   port (val : out std_logic_vector (3 downto 0);
+         ck : std_logic;
+         rst : std_logic);
+end counter;
+
+library ieee;
+use ieee.std_logic_unsigned.all;
+
+architecture bad of counter
+is
+   signal v : std_logic_vector (3 downto 0);
+begin
+   process (ck, rst)
+   begin
+     if rst = '1' then
+        v <= x"0";
+     elsif rising_edge (ck) then
+        if v = "1010" then -- Error
+           v <= x"0";
+        else
+           v <= v + 1;
+        end if;
+     end if;
+   end process;
+
+   val <= v;
+end bad;
+@end example
+
+When you analyze this design, GHDL does not accept it (too long lines
+have been split for readability):
+
+@example
+ghdl -a --ieee=synopsys bad_counter.vhdl
+bad_counter.vhdl:13:14: operator "=" is overloaded
+bad_counter.vhdl:13:14: possible interpretations are:
+../../libraries/ieee/std_logic_1164.v93:69:5: implicit function "="
+    [std_logic_vector, std_logic_vector return boolean]
+../../libraries/synopsys/std_logic_unsigned.vhdl:64:5: function "="
+    [std_logic_vector, std_logic_vector return boolean]
+../translate/ghdldrv/ghdl: compilation error
+@end example
+
+Indeed, the @cite{"="} operator is defined in both packages, and both
+are visible at the place it is used.  The first declaration is an
+implicit one, which occurs when the @cite{std_logic_vector} type is
+declared and is an element to element comparison, the second one is an
+explicit declared function, with the semantic of an unsigned comparison.
+
+With some analyser, the explicit declaration has priority over the implicit
+declaration, and this design can be analyzed without error.  However, this
+is not the rule given by the VHDL LRM, and since GHDL follows these rules,
+it emits an error.
+
+You can force GHDL to use this rule with the @emph{-fexplicit} option.
+@ref{13,,GHDL options}, for more details.
+
+However it is easy to fix this error, by using a selected name:
+
+@example
+library ieee;
+use ieee.std_logic_unsigned.all;
+
+architecture fixed_bad of counter
+is
+   signal v : std_logic_vector (3 downto 0);
+begin
+   process (ck, rst)
+   begin
+     if rst = '1' then
+        v <= x"0";
+     elsif rising_edge (ck) then
+        if ieee.std_logic_unsigned."=" (v, "1010") then
+           v <= x"0";
+        else
+           v <= v + 1;
+        end if;
+     end if;
+   end process;
+
+   val <= v;
+end fixed_bad;
+@end example
+
+It is better to only use the standard packages defined by IEEE, which
+provides the same functionalities:
+
+@example
+library ieee;
+use ieee.numeric_std.all;
+
+architecture good of counter
+is
+   signal v : unsigned (3 downto 0);
+begin
+   process (ck, rst)
+   begin
+     if rst = '1' then
+        v <= x"0";
+     elsif rising_edge (ck) then
+        if v = "1010" then
+           v <= x"0";
+        else
+           v <= v + 1;
+        end if;
+     end if;
+   end process;
+
+   val <= std_logic_vector (v);
+end good;
+@end example
+
+@node IEEE math packages,,IEEE library pitfalls,Invoking GHDL
+@anchor{Invoking_GHDL ieee-math-packages}@anchor{64}
+@section IEEE math packages
+
+
+@geindex Math_Real
+
+@geindex Math_Complex
+
+The @code{ieee} math packages (@code{math_real} and
+@code{math_complex}) provided with @cite{GHDL} are fully compliant with
+the @cite{IEEE} standard.
+
+@node Simulation and runtime,GHDL implementation of VHDL,Invoking GHDL,Top
+@anchor{Simulation_and_runtime simulation-and-runtime}@anchor{19}@anchor{Simulation_and_runtime doc}@anchor{65}@anchor{Simulation_and_runtime id1}@anchor{66}
+@chapter Simulation and runtime
+
+
+@menu
+* Simulation options:: 
+* Debugging VHDL programs:: 
+
+@end menu
+
+@node Simulation options,Debugging VHDL programs,,Simulation and runtime
+@anchor{Simulation_and_runtime simulation-options}@anchor{b}@anchor{Simulation_and_runtime id2}@anchor{67}
+@section Simulation options
+
+
+In most system environments, it is possible to pass options while
+invoking a program.  Contrary to most programming languages, there is no
+standard method in VHDL to obtain the arguments or to set the exit
+status.
+
+In GHDL, it is impossible to pass parameters to your design.  A later version
+could do it through the generics interfaces of the top entity.
+
+However, the GHDL runtime behaviour can be modified with some options; for
+example, it is possible to stop simulation after a certain time.
+
+The exit status of the simulation is @code{EXIT_SUCCESS} (0) if the
+simulation completes, or @code{EXIT_FAILURE} (1) in case of error
+(assertion failure, overflow or any constraint error).
+
+Here is the list of the most useful options.  Some debugging options are
+also available, but not described here.  The @ref{68,,--help} options lists
+all options available, including the debugging one.
+
+@geindex command line option; --assert-level=<LEVEL>
+@anchor{Simulation_and_runtime cmdoption--assert-level}@anchor{69}
+@deffn {Option} @w{-}@w{-}assert@w{-}level=<LEVEL>
+
+Select the assertion level at which an assertion violation stops the
+simulation.  @cite{LEVEL} is the name from the @cite{severity_level}
+enumerated type defined in the @cite{standard} package or the
+@code{none} name.
+
+By default, only assertion violation of severity level @code{failure}
+stops the simulation.
+
+For example, if @cite{LEVEL} was @code{warning}, any assertion violation
+with severity level @code{warning}, @code{error} or @code{failure} would
+stop simulation, but the assertion violation at the @code{note} severity
+level would only display a message.
+
+Option @code{--assert-level=none} prevents any assertion violation to stop
+simulation.
+@end deffn
+
+@geindex command line option; --ieee-asserts=<POLICY>
+@anchor{Simulation_and_runtime cmdoption--ieee-asserts}@anchor{6a}
+@deffn {Option} @w{-}@w{-}ieee@w{-}asserts=<POLICY>
+
+Select how the assertions from @code{ieee} units are
+handled. @cite{POLICY} can be @code{enable} (the default),
+@code{disable} which disables all assertion from @code{ieee} packages
+and @code{disable-at-0} which disables only at start of simulation.
+
+This option can be useful to avoid assertion message from
+@code{ieee.numeric_std} (and other @code{ieee} packages).
+@end deffn
+
+@geindex command line option; --stop-time=<TIME>
+@anchor{Simulation_and_runtime cmdoption--stop-time}@anchor{6b}
+@deffn {Option} @w{-}@w{-}stop@w{-}time=<TIME>
+
+Stop the simulation after @code{TIME}.  @code{TIME} is expressed as a time
+value, @emph{without} any space.  The time is the simulation time, not
+the real clock time.
+
+For example:
+
+@example
+$ ./my_design --stop-time=10ns
+$ ./my_design --stop-time=ps
+@end example
+@end deffn
+
+@geindex command line option; --stop-delta=<N>
+@anchor{Simulation_and_runtime cmdoption--stop-delta}@anchor{6c}
+@deffn {Option} @w{-}@w{-}stop@w{-}delta=<N>
+
+Stop the simulation after @cite{N} delta cycles in the same current time.
+
+@geindex display time
+@end deffn
+
+@geindex command line option; --disp-time
+@anchor{Simulation_and_runtime cmdoption--disp-time}@anchor{6d}
+@deffn {Option} @w{-}@w{-}disp@w{-}time
+
+Display the time and delta cycle number as simulation advances.
+@end deffn
+
+@geindex command line option; --disp-tree[=<KIND>]
+@anchor{Simulation_and_runtime cmdoption--disp-tree}@anchor{6e}
+@deffn {Option} @w{-}@w{-}disp@w{-}tree[=<KIND>]
+
+@geindex display design hierarchy
+
+Display the design hierarchy as a tree of instantiated design entities.
+This may be useful to understand the structure of a complex
+design. @cite{KIND} is optional, but if set must be one of:
+
+
+@itemize *
+
+@item 
+none
+Do not display hierarchy.  Same as if the option was not present.
+
+@item 
+inst
+Display entities, architectures, instances, blocks and generates statements.
+
+@item 
+proc
+Like @code{inst} but also display processes.
+
+@item 
+port
+Like @code{proc} but display ports and signals too.
+If @cite{KIND} is not specified, the hierarchy is displayed with the
+@code{port} mode.
+@end itemize
+@end deffn
+
+@geindex command line option; --no-run
+@anchor{Simulation_and_runtime cmdoption--no-run}@anchor{6f}
+@deffn {Option} @w{-}@w{-}no@w{-}run
+
+Do not simulate, only elaborate.  This may be used with
+@ref{6e,,--disp-tree} to display the tree without simulating the whole
+design.
+@end deffn
+
+@geindex command line option; --vcd=<FILENAME>
+@anchor{Simulation_and_runtime cmdoption--vcd}@anchor{c}
+@deffn {Option} @w{-}@w{-}vcd=<FILENAME>
+@end deffn
+
+@geindex command line option; --vcdgz=<FILENAME>
+@anchor{Simulation_and_runtime cmdoption--vcdgz}@anchor{70}
+@deffn {Option} @w{-}@w{-}vcdgz=<FILENAME>
+
+@geindex vcd
+
+@geindex value change dump
+
+@geindex dump of signals
+
+Option @ref{c,,--vcd} dumps into the VCD file @cite{FILENAME} the signal
+values before each non-delta cycle.  If @cite{FILENAME} is @code{-},
+then the standard output is used, otherwise a file is created or
+overwritten.
+
+The @ref{70,,--vcdgz} option is the same as the @emph{--vcd} option,
+but the output is compressed using the @cite{zlib} (@cite{gzip}
+compression).  However, you can't use the @code{-} filename.
+Furthermore, only one VCD file can be written.
+
+@emph{VCD} (value change dump) is a file format defined
+by the @cite{verilog} standard and used by virtually any wave viewer.
+
+Since it comes from @cite{verilog}, only a few VHDL types can be dumped.  GHDL
+dumps only signals whose base type is of the following:
+
+
+@itemize *
+
+@item 
+types defined in the @code{std.standard} package:
+
+@item 
+@code{bit}
+
+@item 
+@code{bit_vector}
+
+@item 
+types defined in the @code{ieee.std_logic_1164} package:
+
+@item 
+@code{std_ulogic}
+
+@item 
+@code{std_logic} (because it is a subtype of @code{std_ulogic})
+
+@item 
+@code{std_ulogic_vector}
+
+@item 
+@code{std_logic_vector}
+
+@item 
+any integer type
+@end itemize
+
+I have successfully used @cite{gtkwave} to view VCD files.
+
+Currently, there is no way to select signals to be dumped: all signals are
+dumped, which can generate big files.
+
+It is very unfortunate there is no standard or well-known wave file
+format supporting VHDL types.  If you are aware of such a free format,
+please mail me (@ref{71,,Reporting bugs}).
+@end deffn
+
+@geindex command line option; --fst=<FILENAME>
+@anchor{Simulation_and_runtime cmdoption--fst}@anchor{72}
+@deffn {Option} @w{-}@w{-}fst=<FILENAME>
+
+Write the waveforms into a @cite{fst}, that can be displayed by
+@cite{gtkwave}. The @cite{fst} files are much smaller than VCD or
+@cite{GHW} files, but it handles only the same signals as the VCD format.
+@end deffn
+
+@geindex command line option; --wave=<FILENAME>
+@anchor{Simulation_and_runtime cmdoption--wave}@anchor{73}
+@deffn {Option} @w{-}@w{-}wave=<FILENAME>
+
+Write the waveforms into a @cite{ghw} (GHdl Waveform) file.  Currently, all
+the signals are dumped into the waveform file, you cannot select a hierarchy
+of signals to be dumped.
+
+The format of this file was defined by myself and is not yet completely fixed.
+It may change slightly.  The @code{gtkwave} tool can read the GHW files.
+
+Contrary to VCD files, any VHDL type can be dumped into a GHW file.
+@end deffn
+
+@geindex command line option; --sdf=<PATH>=<FILENAME>
+@anchor{Simulation_and_runtime cmdoption--sdf}@anchor{74}
+@deffn {Option} @w{-}@w{-}sdf=<PATH>=<FILENAME>
+
+Do VITAL annotation on @cite{PATH} with SDF file @code{FILENAME}.
+
+@cite{PATH} is a path of instances, separated with @code{.} or @code{/}.
+Any separator can be used.  Instances are component instantiation labels,
+generate labels or block labels.  Currently, you cannot use an indexed name.
+
+Specifying a delay:
+
+@example
+--sdf=min=<PATH>=<FILENAME>
+--sdf=typ=<PATH>=<FILENAME>
+--sdf=max=<PATH>=<FILENAME>
+@end example
+
+If the option contains a type of delay, that is @code{min=},
+@code{typ=} or @code{max=}, the annotator use respectively minimum,
+typical or maximum values.  If the option does not contain a type of delay,
+the annotator use the typical delay.
+
+See @ref{75,,Backannotation}, for more details.
+@end deffn
+
+@geindex command line option; --help
+@anchor{Simulation_and_runtime cmdoption--help}@anchor{68}
+@deffn {Option} @w{-}@w{-}help
+
+Display a short description of the options accepted by the runtime library.
+@end deffn
+
+@node Debugging VHDL programs,,Simulation options,Simulation and runtime
+@anchor{Simulation_and_runtime debugging-vhdl-programs}@anchor{76}
+@section Debugging VHDL programs
+
+
+@geindex debugging
+
+@geindex `__ghdl_fatal`
+
+Debugging VHDL programs using @cite{GDB} is possible only on GNU/Linux systems.
+
+@cite{GDB} is a general purpose debugger for programs compiled by @cite{GCC}.
+Currently, there is no VHDL support for @cite{GDB}.  It may be difficult
+to inspect variables or signals in @cite{GDB}, however, @cite{GDB} is
+still able to display the stack frame in case of error or to set a breakpoint
+at a specified line.
+
+@cite{GDB} can be useful to precisely catch a runtime error, such as indexing
+an array beyond its bounds.  All error check subprograms call the
+@cite{__ghdl_fatal} procedure.  Therefore, to catch runtime error, set
+a breakpoint like this:
+
+@quotation
+
+(gdb) break __ghdl_fatal
+@end quotation
+
+When the breakpoint is hit, use the @cite{where} or @cite{bt} command to
+display the stack frames.
+
+@node GHDL implementation of VHDL,GHDL implementation of VITAL,Simulation and runtime,Top
+@anchor{GHDL_implementation_of_VHDL doc}@anchor{77}@anchor{GHDL_implementation_of_VHDL ghdl-implementation-of-vhdl}@anchor{78}
+@chapter GHDL implementation of VHDL
+
+
+This chapter describes several implementation defined aspect of VHDL in GHDL.
+
+@menu
+* VHDL standards:: 
+* PSL implementation:: 
+* Source representation:: 
+* Library database:: 
+* Top entity:: 
+* Using vendor libraries:: 
+* Interfacing to other languages:: 
+
+@end menu
+
+@node VHDL standards,PSL implementation,,GHDL implementation of VHDL
+@anchor{GHDL_implementation_of_VHDL vhdl-standards}@anchor{29}@anchor{GHDL_implementation_of_VHDL id1}@anchor{79}
+@section VHDL standards
+
+
+@geindex VHDL standards
+
+@geindex IEEE 1076
+
+@geindex IEEE 1076a
+
+@geindex 1076
+
+@geindex 1076a
+
+@geindex v87
+
+@geindex v93
+
+@geindex v93c
+
+@geindex v00
+
+@geindex v02
+
+This is very unfortunate, but there are many versions of the VHDL
+language, and they aren't backward compatible.
+
+The VHDL language was first standardized in 1987 by IEEE as IEEE 1076-1987, and
+is commonly referred as VHDL-87. This is certainly the most important version,
+since most of the VHDL tools are still based on this standard.
+
+Various problems of this first standard have been analyzed by experts groups
+to give reasonable ways of interpreting the unclear portions of the standard.
+
+VHDL was revised in 1993 by IEEE as IEEE 1076-1993.  This revision is still
+well-known.
+
+Unfortunately, VHDL-93 is not fully compatible with VHDL-87, i.e. some perfectly
+valid VHDL-87 programs are invalid VHDL-93 programs.  Here are some of the
+reasons:
+
+
+@itemize *
+
+@item 
+the syntax of file declaration has changed (this is the most visible source
+of incompatibility),
+
+@item 
+new keywords were introduced (group, impure, inertial, literal,
+postponed, pure, reject, rol, ror, shared, sla, sll, sra, srl,
+unaffected, xnor),
+
+@item 
+some dynamic behaviours have changed (the concatenation is one of them),
+
+@item 
+rules have been added.
+@end itemize
+
+Shared variables were replaced by protected types in the 2000 revision of
+the VHDL standard.  This modification is also known as 1076a.  Note that this
+standard is not fully backward compatible with VHDL-93, since the type of a
+shared variable must now be a protected type (there was no such restriction
+before).
+
+Minors corrections were added by the 2002 revision of the VHDL standard.  This
+revision is not fully backward compatible with VHDL-00 since, for example,
+the value of the @cite{'instance_name} attribute has slightly changed.
+
+You can select the VHDL standard expected by GHDL with the
+@code{--std=VER} option, where @code{VER} is one of the left column of the
+table below:
+
+
+@table @asis
+
+@item 87
+
+Select VHDL-87 standard as defined by IEEE 1076-1987.  LRM bugs corrected by
+later revisions are taken into account.
+
+@item 93
+
+Select VHDL-93; VHDL-87 file declarations are not accepted.
+
+@item 93c
+
+Select VHDL-93 standard with relaxed rules:
+
+
+@itemize *
+
+@item 
+VHDL-87 file declarations are accepted;
+
+@item 
+default binding indication rules of VHDL-02 are used.  Default binding rules
+are often used, but they are particularly obscure before VHDL-02.
+@end itemize
+
+@item 00
+
+Select VHDL-2000 standard, which adds protected types.
+
+@item 02
+
+Select VHDL-2002 standard
+
+@item 08
+
+Select VHDL-2008 standard (partially implemented).
+@end table
+
+You cannot mix VHDL-87 and VHDL-93 units.  A design hierarchy must have been
+completely analyzed using either the 87 or the 93 version of the VHDL standard.
+
+@node PSL implementation,Source representation,VHDL standards,GHDL implementation of VHDL
+@anchor{GHDL_implementation_of_VHDL id2}@anchor{7a}@anchor{GHDL_implementation_of_VHDL psl-implementation}@anchor{2f}
+@section PSL implementation
+
+
+GHDL understands embedded PSL annotations in VHDL files, but not in
+separate files.
+
+As PSL annotations are embedded within comments, you must analyze and elaborate
+your design with option @emph{-fpsl} to enable PSL annotations.
+
+A PSL assertion statement must appear within a comment that starts
+with the @cite{psl} keyword.  The keyword must be followed (on the
+same line) by a PSL keyword such as @cite{assert} or @cite{default}.
+To continue a PSL statement on the next line, just start a new comment.
+
+A PSL statement is considered as a process.  So it is not allowed within
+a process.
+
+All PSL assertions must be clocked (GHDL doesn't support unclocked assertion).
+Furthermore only one clock per assertion is allowed.
+
+You can either use a default clock like this:
+
+@example
+-- psl default clock is rising_edge (CLK);
+-- psl assert always
+--   a -> eventually! b;
+@end example
+
+or use a clocked expression (note the use of parenthesis):
+
+@example
+-- psl assert (always a -> next[3](b)) @@rising_edge (clk);
+@end example
+
+Of course only the simple subset of PSL is allowed.
+
+Currently the built-in functions are not implemented.
+
+@node Source representation,Library database,PSL implementation,GHDL implementation of VHDL
+@anchor{GHDL_implementation_of_VHDL source-representation}@anchor{7b}
+@section Source representation
+
+
+According to the VHDL standard, design units (i.e. entities,
+architectures, packages, package bodies and configurations) may be
+independently analyzed.
+
+Several design units may be grouped into a design file.
+
+In GHDL, a system file represents a design file.  That is, a file compiled by
+GHDL may contain one or more design units.
+
+It is common to have several design units in a design file.
+
+GHDL does not impose any restriction on the name of a design file
+(except that the filename may not contain any control character or
+spaces).
+
+GHDL do not keep a binary representation of the design units analyzed like
+other VHDL analyzers.  The sources of the design units are re-read when
+needed (for example, an entity is re-read when one of its architecture is
+analyzed).  Therefore, if you delete or modify a source file of a unit
+analyzed, GHDL will refuse to use it.
+
+@node Library database,Top entity,Source representation,GHDL implementation of VHDL
+@anchor{GHDL_implementation_of_VHDL library-database}@anchor{7c}@anchor{GHDL_implementation_of_VHDL id3}@anchor{7d}
+@section Library database
+
+
+Each design unit analyzed is placed into a design library.  By default,
+the name of this design library is @code{work}; however, this can be
+changed with the @code{--work=NAME} option of GHDL.
+
+To keep the list of design units in a design library, GHDL creates
+library files.  The name of these files is @code{NAME-objVER.cf}, where
+@cite{NAME} is the name of the library, and @cite{VER} the VHDL version (87
+or 93) used to analyze the design units.
+
+You don't have to know how to read a library file.  You can display it
+using the @emph{-d} of @cite{ghdl}.  The file contains the name of the
+design units, as well as the location and the dependencies.
+
+The format may change with the next version of GHDL.
+
+@node Top entity,Using vendor libraries,Library database,GHDL implementation of VHDL
+@anchor{GHDL_implementation_of_VHDL top-entity}@anchor{16}@anchor{GHDL_implementation_of_VHDL id4}@anchor{7e}
+@section Top entity
+
+
+There are some restrictions on the entity being at the apex of a design
+hierarchy:
+
+
+@itemize *
+
+@item 
+The generic must have a default value, and the value of a generic is its
+default value;
+
+@item 
+The ports type must be constrained.
+@end itemize
+
+@node Using vendor libraries,Interfacing to other languages,Top entity,GHDL implementation of VHDL
+@anchor{GHDL_implementation_of_VHDL using-vendor-libraries}@anchor{7f}
+@section Using vendor libraries
+
+
+Many vendors libraries have been analyzed with GHDL.  There are
+usually no problems.  Be sure to use the @code{--work=} option.
+However, some problems have been encountered.
+
+GHDL follows the VHDL LRM (the manual which defines VHDL) more
+strictly than other VHDL tools.  You could try to relax the
+restrictions by using the @code{--std=93c}, @ref{2c,,-fexplicit},
+@ref{2d,,-frelaxed-rules} and @code{--warn-no-vital-generic}.
+
+@node Interfacing to other languages,,Using vendor libraries,GHDL implementation of VHDL
+@anchor{GHDL_implementation_of_VHDL interfacing-to-other-languages}@anchor{80}
+@section Interfacing to other languages
+
+
+@geindex interfacing
+
+@geindex other languages
+
+@geindex foreign
+
+@geindex VHPI
+
+@geindex VHPIDIRECT
+
+Interfacing with foreign languages is possible only on GNU/Linux systems.
+
+You can define a subprogram in a foreign language (such as @cite{C} or
+@cite{Ada}) and import it in a VHDL design.
+
+@menu
+* Foreign declarations:: 
+* Restrictions on foreign declarations:: 
+* Linking with foreign object files:: 
+* Starting a simulation from a foreign program:: 
+* Linking with Ada:: 
+* Using GRT from Ada:: 
+
+@end menu
+
+@node Foreign declarations,Restrictions on foreign declarations,,Interfacing to other languages
+@anchor{GHDL_implementation_of_VHDL foreign-declarations}@anchor{81}
+@subsection Foreign declarations
+
+
+Only subprograms (functions or procedures) can be imported, using the foreign
+attribute.  In this example, the @cite{sin} function is imported:
+
+@example
+package math is
+  function sin (v : real) return real;
+  attribute foreign of sin : function is "VHPIDIRECT sin";
+end math;
+
+package body math is
+  function sin (v : real) return real is
+  begin
+    assert false severity failure;
+  end sin;
+end math;
+@end example
+
+A subprogram is made foreign if the @cite{foreign} attribute decorates
+it.  This attribute is declared in the 1993 revision of the
+@code{std.standard} package.  Therefore, you cannot use this feature in
+VHDL 1987.
+
+The decoration is achieved through an attribute specification.  The
+attribute specification must be in the same declarative part as the
+subprogram and must be after it.  This is a general rule for specifications.
+The value of the specification must be a locally static string.
+
+Even when a subprogram is foreign, its body must be present.  However, since
+it won't be called, you can made it empty or simply but an assertion.
+
+The value of the attribute must start with @code{VHPIDIRECT} (an
+upper-case keyword followed by one or more blanks).  The linkage name of the
+subprogram follows.
+
+@node Restrictions on foreign declarations,Linking with foreign object files,Foreign declarations,Interfacing to other languages
+@anchor{GHDL_implementation_of_VHDL restrictions-on-foreign-declarations}@anchor{82}@anchor{GHDL_implementation_of_VHDL id5}@anchor{83}
+@subsection Restrictions on foreign declarations
+
+
+Any subprogram can be imported.  GHDL puts no restrictions on foreign
+subprograms.  However, the representation of a type or of an interface in a
+foreign language may be obscure.  Most of non-composite types are easily imported:
+
+
+@table @asis
+
+@item @emph{integer types}
+
+They are represented on a 32 bits word.  This generally corresponds to
+@cite{int} for @cite{C} or @cite{Integer} for @cite{Ada}.
+
+@item @emph{physical types}
+
+They are represented on a 64 bits word.  This generally corresponds to the
+@cite{long long} for @cite{C} or @cite{Long_Long_Integer} for @cite{Ada}.
+
+@item @emph{floating point types}
+
+They are represented on a 64 bits floating point word.  This generally
+corresponds to @cite{double} for @cite{C} or @cite{Long_Float} for @cite{Ada}.
+
+@item @emph{enumeration types}
+
+They are represented on 8 bits or 32 bits word, if the number of literals is
+greater than 256.  There is no corresponding C types, since arguments are
+not promoted.
+@end table
+
+Non-composite types are passed by value.  For the @cite{in} mode, this
+corresponds to the @cite{C} or @cite{Ada} mechanism.  The @cite{out} and
+@cite{inout} interfaces of non-composite types are gathered in a record
+and this record is passed by reference as the first argument to the
+subprogram.  As a consequence, you shouldn't use @cite{in} and
+@cite{inout} modes in foreign subprograms, since they are not portable.
+
+Records are represented like a @cite{C} structure and are passed by reference
+to subprograms.
+
+Arrays with static bounds are represented like a @cite{C} array, whose
+length is the number of elements, and are passed by reference to subprograms.
+
+Unconstrained array are represented by a fat pointer.  Do not use unconstrained
+arrays in foreign subprograms.
+
+Accesses to an unconstrained array is a fat pointer.  Other accesses correspond to an address and are passed to a subprogram like other non-composite types.
+
+Files are represented by a 32 bits word, which corresponds to an index
+in a table.
+
+@node Linking with foreign object files,Starting a simulation from a foreign program,Restrictions on foreign declarations,Interfacing to other languages
+@anchor{GHDL_implementation_of_VHDL id6}@anchor{84}@anchor{GHDL_implementation_of_VHDL linking-with-foreign-object-files}@anchor{85}
+@subsection Linking with foreign object files
+
+
+You may add additional files or options during the link using the
+@emph{-Wl,} of @cite{GHDL}, as described in @ref{15,,Elaboration command}.
+For example:
+
+@example
+ghdl -e -Wl,-lm math_tb
+@end example
+
+will create the @code{math_tb} executable with the @code{lm} (mathematical)
+library.
+
+Note the @code{c} library is always linked with an executable.
+
+@node Starting a simulation from a foreign program,Linking with Ada,Linking with foreign object files,Interfacing to other languages
+@anchor{GHDL_implementation_of_VHDL id7}@anchor{86}@anchor{GHDL_implementation_of_VHDL starting-a-simulation-from-a-foreign-program}@anchor{87}
+@subsection Starting a simulation from a foreign program
+
+
+You may run your design from an external program.  You just have to call
+the @code{ghdl_main} function which can be defined:
+
+in C:
+
+@example
+extern int ghdl_main (int argc, char **argv);
+@end example
+
+in Ada:
+
+@example
+with System;
+...
+function Ghdl_Main (Argc : Integer; Argv : System.Address)
+   return Integer;
+pragma import (C, Ghdl_Main, "ghdl_main");
+@end example
+
+This function must be called once, and returns 0 at the end of the simulation.
+In case of failure, this function does not return.  This has to be fixed.
+
+@node Linking with Ada,Using GRT from Ada,Starting a simulation from a foreign program,Interfacing to other languages
+@anchor{GHDL_implementation_of_VHDL linking-with-ada}@anchor{88}@anchor{GHDL_implementation_of_VHDL id8}@anchor{89}
+@subsection Linking with Ada
+
+
+As explained previously in @ref{87,,Starting a simulation from a foreign program},
+you can start a simulation from an @cite{Ada} program.  However the build
+process is not trivial: you have to elaborate your @cite{Ada} program and your
+@cite{VHDL} design.
+
+First, you have to analyze all your design files.  In this example, we
+suppose there is only one design file, @code{design.vhdl}.
+
+@example
+$ ghdl -a design.vhdl
+@end example
+
+Then, bind your design.  In this example, we suppose the entity at the
+design apex is @code{design}.
+
+@example
+$ ghdl --bind design
+@end example
+
+Finally, compile, bind your @cite{Ada} program at link it with your @cite{VHDL}
+design:
+
+@example
+$ gnatmake my_prog -largs `ghdl --list-link design`
+@end example
+
+@node Using GRT from Ada,,Linking with Ada,Interfacing to other languages
+@anchor{GHDL_implementation_of_VHDL using-grt-from-ada}@anchor{8a}
+@subsection Using GRT from Ada
+
+
+@cartouche
+@quotation Warning 
+This topic is only for advanced users knowing how to use @cite{Ada}
+and @cite{GNAT}.  This is provided only for reference, I have tested
+this once before releasing @cite{GHDL} 0.19 but this is not checked at
+each release.
+@end quotation
+@end cartouche
+
+The simulator kernel of @cite{GHDL} named @emph{GRT} is written in
+@cite{Ada95} and contains a very light and slightly adapted version
+of @cite{VHPI}.  Since it is an @cite{Ada} implementation it is
+called @emph{AVHPI}. Although being tough, you may interface to @cite{AVHPI}.
+
+For using @cite{AVHPI}, you need the sources of @cite{GHDL} and to recompile
+them (at least the @cite{GRT} library).  This library is usually compiled with
+a @cite{No_Run_Time} pragma, so that the user does not need to install the
+@cite{GNAT} runtime library.  However, you certainly want to use the usual
+runtime library and want to avoid this pragma.  For this, reset the
+@cite{GRT_PRAGMA_FLAG} variable.
+
+@example
+$ make GRT_PRAGMA_FLAG= grt-all
+@end example
+
+Since @cite{GRT} is a self-contained library, you don't want
+@cite{gnatlink} to fetch individual object files (furthermore this
+doesn't always work due to tricks used in @cite{GRT}).  For this,
+remove all the object files and make the @code{.ali} files read-only.
+
+@example
+$ rm *.o
+$ chmod -w *.ali
+@end example
+
+You may then install the sources files and the @code{.ali} files.  I have never
+tested this step.
+
+You are now ready to use it.
+
+For example, here is an example, @code{test_grt.adb} which displays the top
+level design name.
+
+@example
+with System; use System;
+with Grt.Avhpi; use Grt.Avhpi;
+with Ada.Text_IO; use Ada.Text_IO;
+with Ghdl_Main;
+
+procedure Test_Grt is
+   --  VHPI handle.
+   H : VhpiHandleT;
+   Status : Integer;
+
+   --  Name.
+   Name : String (1 .. 64);
+   Name_Len : Integer;
+begin
+   --  Elaborate and run the design.
+   Status := Ghdl_Main (0, Null_Address);
+
+   --  Display the status of the simulation.
+   Put_Line ("Status is " & Integer'Image (Status));
+
+   --  Get the root instance.
+   Get_Root_Inst(H);
+
+   --  Disp its name using vhpi API.
+   Vhpi_Get_Str (VhpiNameP, H, Name, Name_Len);
+   Put_Line ("Root instance name: " & Name (1 .. Name_Len));
+end Test_Grt;
+@end example
+
+First, analyze and bind your design:
+
+@example
+$ ghdl -a counter.vhdl
+$ ghdl --bind counter
+@end example
+
+Then build the whole:
+
+@example
+$ gnatmake test_grt -aL`grt_ali_path` -aI`grt_src_path` -largs
+ `ghdl --list-link counter`
+@end example
+
+Finally, run your design:
+
+@example
+$ ./test_grt
+Status is  0
+Root instance name: counter
+@end example
+
+@node GHDL implementation of VITAL,Flaws and bugs report,GHDL implementation of VHDL,Top
+@anchor{GHDL_implementation_of_VITAL ghdl-implementation-of-vital}@anchor{8b}@anchor{GHDL_implementation_of_VITAL doc}@anchor{8c}
+@chapter GHDL implementation of VITAL
+
+
+@geindex VITAL
+
+@geindex IEEE 1076.4
+
+@geindex 1076.4
+
+This chapter describes how VITAL is implemented in GHDL.  Support of VITAL is
+really in a preliminary stage.  Do not expect too much of it as now.
+
+@menu
+* VITAL packages:: 
+* VHDL restrictions for VITAL:: 
+* Backannotation:: 
+* Negative constraint calculation:: 
+
+@end menu
+
+@node VITAL packages,VHDL restrictions for VITAL,,GHDL implementation of VITAL
+@anchor{GHDL_implementation_of_VITAL vital-packages}@anchor{2b}@anchor{GHDL_implementation_of_VITAL id1}@anchor{8d}
+@section VITAL packages
+
+
+The VITAL standard or IEEE 1076.4 was first published in 1995, and revised in
+2000.
+
+The version of the VITAL packages depends on the VHDL standard.  VITAL
+1995 packages are used with the VHDL 1987 standard, while VITAL 2000
+packages are used with other standards.  This choice is based on the
+requirements of VITAL: VITAL 1995 requires the models follow the VHDL
+1987 standard, while VITAL 2000 requires the models follow VHDL 1993.
+
+The VITAL 2000 packages were slightly modified so that they conform to
+the VHDL 1993 standard (a few functions are made pure and a few one
+impure).
+
+@node VHDL restrictions for VITAL,Backannotation,VITAL packages,GHDL implementation of VITAL
+@anchor{GHDL_implementation_of_VITAL id2}@anchor{8e}@anchor{GHDL_implementation_of_VITAL vhdl-restrictions-for-vital}@anchor{32}
+@section VHDL restrictions for VITAL
+
+
+The VITAL standard (partially) implemented is the IEEE 1076.4 standard
+published in 1995.
+
+This standard defines restriction of the VHDL language usage on VITAL
+model.  A @emph{VITAL model} is a design unit (entity or architecture)
+decorated by the @cite{VITAL_Level0} or @cite{VITAL_Level1} attribute.
+These attributes are defined in the @cite{ieee.VITAL_Timing} package.
+
+Currently, only VITAL level 0 checks are implemented.  VITAL level 1 models
+can be analyzed, but GHDL doesn't check they comply with the VITAL standard.
+
+Moreover, GHDL doesn't check (yet) that timing generics are not read inside
+a VITAL level 0 model prior the VITAL annotation.
+
+The analysis of a non-conformant VITAL model fails.  You can disable the
+checks of VITAL restrictions with the @emph{--no-vital-checks}.  Even when
+restrictions are not checked, SDF annotation can be performed.
+
+@node Backannotation,Negative constraint calculation,VHDL restrictions for VITAL,GHDL implementation of VITAL
+@anchor{GHDL_implementation_of_VITAL backannotation}@anchor{75}@anchor{GHDL_implementation_of_VITAL id3}@anchor{8f}
+@section Backannotation
+
+
+@geindex SDF
+
+@emph{Backannotation} is the process of setting VITAL generics with timing
+information provided by an external files.
+
+The external files must be SDF (Standard Delay Format) files.  GHDL
+supports a tiny subset of SDF version 2.1, other version number can be
+used, provided no features added by the next version are used.
+
+Hierarchical instance names are not supported. However you can use a list of
+instances.  If there is no instance, the top entity will be annotated and
+the celltype must be the name of the top entity.  If there is at least one
+instance, the last instance name must be a component instantiation label, and
+the celltype must be the name of the component declaration instantiated.
+
+Instances being annotated are not required to be VITAL compliant.  However
+generics being annotated must follow rules of VITAL (e.g., type must be a
+suitable vital delay type).
+
+Currently, only timing constraints applying on a timing generic of type
+@cite{VitalDelayType01} has been implemented.  This SDF annotator is
+just a proof of concept.  Features will be added with the following GHDL
+release.
+
+@node Negative constraint calculation,,Backannotation,GHDL implementation of VITAL
+@anchor{GHDL_implementation_of_VITAL negative-constraint-calculation}@anchor{90}
+@section Negative constraint calculation
+
+
+Negative constraint delay adjustment are necessary to handle negative
+constraint such as a negative setup time.  This step is defined in the VITAL
+standard and should occur after backannotation.
+
+GHDL does not do negative constraint calculation.  It fails to handle models
+with negative constraint.  I hope to be able to add this phase soon.
+
+@node Flaws and bugs report,Copyrights,GHDL implementation of VITAL,Top
+@anchor{Flaws_and_bugs_report doc}@anchor{91}@anchor{Flaws_and_bugs_report flaws-and-bugs-report}@anchor{92}
+@chapter Flaws and bugs report
+
+
+Despite all the testing and already reported issues, you can find bugs
+or propose enhancements.
+
+@quotation
+@anchor{Flaws_and_bugs_report reporting-bugs}@anchor{71}
+@end quotation
+
+@menu
+* Reporting bugs:: 
+* Future improvements:: 
+
+@end menu
+
+@node Reporting bugs,Future improvements,,Flaws and bugs report
+@anchor{Flaws_and_bugs_report id1}@anchor{93}
+@section Reporting bugs
+
+
+In order to improve GHDL, we welcome bugs report and suggestions for
+any aspect of GHDL.  Please create an issue on
+@indicateurl{https://github.com/tgingold/ghdl/issues}
+
+If the compiler crashes, this is a bug.  Reliable tools never crash.
+
+If your compiled VHDL executable crashes, this may be a bug at
+runtime or the code produced may be wrong.  However, since VHDL
+has a notion of pointers, an erroneous VHDL program (using invalid
+pointers for example) may crash.
+
+If the compiler emits an error message for a perfectly valid input or
+does not emit an error message for an invalid input, this may be a bug.
+Please send the input file and what you expected.  If you know the LRM
+well enough, please specify the paragraph which has not been well
+implemented.  If you don't know the LRM, maybe your bug report will be
+rejected simply because there is no bug.  In the latter case, it may be
+difficult to discuss the issue; and comparisons with other VHDL tools
+is not a very strong argument.
+
+If a compiler message is not clear enough for you, please tell me.  The
+error messages can be improved, but I have not enough experience with
+them.
+
+If you have found a mistake in the manual, please send a comment.  If
+you have not understood some parts of this manual, please tell me.
+English is not my mother tongue, so this manual may not be well-written.
+Again, rewriting part of it is a good way to improve it.
+
+If you send a @cite{VHDL} file producing a bug, it is a good idea to try
+to make it as short as possible.  It is also a good idea to make it
+looking like a test: write a comment which explains whether the file
+should compile, and if yes, whether or not it should run successfully.
+In the latter case, an assert statement should finish the test; the
+severity level note indicates success, while a severity level failure
+indicates failure.
+
+For bug reports, please include enough information for the maintainers to
+reproduce the problem. This includes:
+
+
+@itemize *
+
+@item 
+the version of @cite{GHDL} (you can get it with @code{ghdl --version}).
+
+@item 
+the operating system
+
+@item 
+whether you have built @cite{GHDL} from sources or used the binary
+distribution.
+
+@item 
+the content of the input files
+
+@item 
+a description of the problem and samples of any erroneous input
+
+@item 
+anything else that you think would be helpful.
+@end itemize
+
+@node Future improvements,,Reporting bugs,Flaws and bugs report
+@anchor{Flaws_and_bugs_report future-improvements}@anchor{94}
+@section Future improvements
+
+
+I have several axes for @cite{GHDL} improvements:
+
+
+@itemize *
+
+@item 
+Documentation.
+
+@item 
+Better diagnostics messages (warning and error).
+
+@item 
+Full support of VHDL-2008.
+
+@item 
+Optimization (simulation speed).
+
+@item 
+Graphical tools (to see waves and to debug)
+
+@item 
+Style checks
+
+@item 
+VITAL acceleration
+@end itemize
+
+@node Copyrights,Indices and tables,Flaws and bugs report,Top
+@anchor{Copyrights copyrights}@anchor{95}@anchor{Copyrights doc}@anchor{96}
+@chapter Copyrights
+
+
+The GHDL front-end, the @code{std.textio} package and the runtime
+library (@code{grt}) are copyrighted Tristan Gingold, come with @strong{absolutely
+no warranty}, and are distributed under the conditions of the General
+Public License.
+
+The @code{ieee.numeric_bit} and @code{ieee.numeric_std} packages are
+copyrighted by the IEEE.  The source files may be distributed without
+change, except as permitted by the standard.
+
+This source file may not be
+sold or distributed for profit.  See the source file and the IEEE 1076.3
+standard for more information.
+
+The @code{ieee.std_logic_1164}, @code{ieee.Math_Real} and
+@code{ieee.Math_Complex} packages are copyrighted by the IEEE.  See
+source files for more information.
+
+The @code{ieee.VITAL_Primitives}, @code{ieee.VITAL_Timing} and
+@code{ieee.VITAL_Memory} packages are copyrighted by IEEE.  See source
+file and the IEEE 1076.4 standards for more information.
+
+The packages @code{std_logic_arith},
+@code{std_logic_signed}, @code{std_logic_unsigned} and
+@code{std_logic_textio} contained in the @code{synopsys} directory are
+copyrighted by Synopsys, Inc.  The source files may be used and
+distributed without restriction provided that the copyright statements
+are not removed from the files and that any derivative work contains the
+copyright notice.  See the source files for more information.
+
+The package @code{std_logic_arith} contained in the @code{mentor}
+directory is copyrighted by Mentor Graphics.  The source files may be
+distributed in whole without restriction provided that the copyright
+statement is not removed from the file and that any derivative work
+contains this copyright notice.  See the source files for more information.
+
+As a consequence of the runtime copyright, you may not be allowed to
+distribute an executable produced by @cite{GHDL} without the VHDL
+sources.  To my mind, this is not a real restriction, since there is no
+points in distributing VHDL executable.  Please, send a comment
+(@ref{71,,Reporting bugs}) if you don't like this policy.
+
+@node Indices and tables,Index,Copyrights,Top
+@anchor{index indices-and-tables}@anchor{97}
+@unnumbered Indices and tables
+
+
+
+@itemize *
+
+@item 
+genindex
+
+@item 
+search
+@end itemize
+
+@node Index,,Indices and tables,Top
+@unnumbered Index
+
+
+@printindex ge
+
+
+@c %**end of body
+@bye