update doc (synth, overview, generics, etc.) (#1205)

* doc: extend info about setting generics through the CLI

* doc: rename 'Command Reference' to 'Additional Command Reference'

* doc: use '``' instead of ':samp:'

* doc: update info about synthesis

* doc: add references to sources in internals/Overview

* doc: add diagram to internals/Overview

3 files changed, 2 insertions, 10 deletions

diff --git a/doc/development/Documentation.rst b/doc/development/Documentation.rst
index 2ae76ff5e..364986542 100644
--- a/doc/development/Documentation.rst
+++ b/doc/development/Documentation.rst
@@ -3,7 +3,7 @@
 Documentation
 #############
 
-* Development/Synthesis. Synthesis, ghdlsynth-beta, formal verification, etc. Copy the 'Usage' section from ghdlsynth's README (https://github.com/1138-4EB/ghdlsynth-beta#usage).
+* Using/Synthesis: formal verification, etc.
 * Development/libghdl. How to interact with GHDL through ``libghdl`` and/or ``libghdl-py``.
 * Development/Related Projects. Brief discussion about similarities/differences with other open source projects such as rust_hdl or pyVHDLParser.
 * Usage/Docker. Probably copy/convert :file:`README.md` and :file:`USE_CASES.md` in ghdl/docker :ghdlsharp:`166`.
diff --git a/doc/development/GSOC.rst b/doc/development/GSOC.rst
index 813a2aa64..723afb832 100644
--- a/doc/development/GSOC.rst
+++ b/doc/development/GSOC.rst
@@ -8,7 +8,7 @@ This page contains ideas for enhancing GHDL that can fit internship programs, su
 VHDL frontend for Yosys
 =======================
 
-`Yosys <https://github.com/YosysHQ/yosys>`_ is an open-source synthesis tool with built-in Verilog support and partial SystemVerilog support. `ghdlsynth-beta <https://github.com/tgingold/ghdlsynth-beta>`_ is an experimental plugin for Yosys that allows to use GHDL (precisely, `libghdl <https://github.com/ghdl/ghdl#project-structure>`_) as a frontend for Yosys. Although functional, :ref:`DEV:Synthesis` is work in progress: multiple features are not supported yet, and others need to be tested for bugs.
+`Yosys <https://github.com/YosysHQ/yosys>`_ is an open-source synthesis tool with built-in Verilog support and partial SystemVerilog support. :ref:`Synth:plugin` is an experimental plugin for Yosys that allows to use GHDL. Although functional, :ref:`USING:Synthesis` is work in progress: multiple features are not supported yet, and others need to be tested for bugs.
 
 .. NOTE::
     * `FOSSI GSOC 2019 | VHDL front-end for Yosys <https://fossi-foundation.org/gsoc19-ideas.html#vhdl-front-end--for-yosys>`_
diff --git a/doc/development/Synthesis.rst b/doc/development/Synthesis.rst
deleted file mode 100644
index bcd23ff70..000000000
--- a/doc/development/Synthesis.rst
+++ /dev/null
@@ -1,8 +0,0 @@
-.. _DEV:Synthesis:
-
-Synthesis
-#########
-
-There is an experimental command (``--synth``) to generate RTL netlists (the format, VHDL or EDIF, is yet to be defined) from synthesisable code. For command ``--synth`` to be available, GHDL must be configured/built with option ``--enable-synth`` (GCC 8.1>= required, due to some new GNAT features which are only available in recent releases). Since this is a proof-of-concept, the output is mostly a dump of an internal structure for now. Therefore, it is not very useful, except for debugging.
-
-Moreover, `ghdlsynth <https://github.com/tgingold/ghdlsynth-beta>`_ is a complementary repository that lets GHDL to be loaded by `yosys <http://www.clifford.at/yosys/>`_ as a frontend plugin module, in order to generate bitstreams for some FPGA devices.