testsuite/gna: add a test for #1262

5 files changed, 106 insertions, 0 deletions

diff --git a/testsuite/gna/issue1262/ent.vhdl b/testsuite/gna/issue1262/ent.vhdl
new file mode 100644
index 000000000..c71cc8330
--- /dev/null
+++ b/testsuite/gna/issue1262/ent.vhdl
@@ -0,0 +1,17 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ent is
+  generic(
+    WIDTH: integer;
+    package slv_pkg is new work.slv generic map(N => WIDTH));
+  port (
+    o_slv: out slv_pkg.slv_t);
+end ent;
+
+architecture beh of ent is
+  constant ones : std_logic_vector(WIDTH-1 downto 0) := (others => '1');
+begin
+  o_slv <= ones;
+end architecture beh;
+
diff --git a/testsuite/gna/issue1262/pkg_slv.vhdl b/testsuite/gna/issue1262/pkg_slv.vhdl
new file mode 100644
index 000000000..a778f9f23
--- /dev/null
+++ b/testsuite/gna/issue1262/pkg_slv.vhdl
@@ -0,0 +1,9 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+package slv is
+	generic(
+		N: integer
+	);
+	subtype slv_t is std_logic_vector(N-1 downto 0);
+end package;
diff --git a/testsuite/gna/issue1262/tb.vhdl b/testsuite/gna/issue1262/tb.vhdl
new file mode 100644
index 000000000..fcf1bdf03
--- /dev/null
+++ b/testsuite/gna/issue1262/tb.vhdl
@@ -0,0 +1,38 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity tb is
+end entity;
+
+architecture test of tb is
+	constant w : integer := 3;
+
+	package slv_tb_pkg is new work.slv generic map(N => w);
+
+	component ent
+		generic(
+			WIDTH: integer
+		);
+		port (
+			o_slv: out slv_tb_pkg.slv_t
+		);
+	end component ent;
+
+	signal s_out : std_logic_vector(w-1 downto 0);
+begin
+	e : ent
+		generic map(
+			WIDTH => w
+		)
+		port map(
+			o_slv => s_out
+		);
+
+	process
+	begin
+		wait for 1 ns;
+		report integer'image(to_integer(unsigned(s_out)));
+		wait;
+	end process;
+end architecture test;
diff --git a/testsuite/gna/issue1262/tb2.vhdl b/testsuite/gna/issue1262/tb2.vhdl
new file mode 100644
index 000000000..a5ca856b7
--- /dev/null
+++ b/testsuite/gna/issue1262/tb2.vhdl
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity tb2 is
+end entity;
+
+architecture test of tb2 is
+	constant w : integer := 4;
+	signal s_out : std_logic_vector(w-1 downto 0);
+begin
+	e : entity work.ent
+		generic map(
+			WIDTH => w
+		)
+		port map(
+			o_slv => s_out
+		);
+
+	process
+	begin
+		wait for 1 ns;
+		report integer'image(to_integer(unsigned(s_out)));
+		wait;
+	end process;
+end architecture test;
diff --git a/testsuite/gna/issue1262/testsuite.sh b/testsuite/gna/issue1262/testsuite.sh
new file mode 100755
index 000000000..89184db62
--- /dev/null
+++ b/testsuite/gna/issue1262/testsuite.sh
@@ -0,0 +1,16 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+analyze pkg_slv.vhdl
+analyze ent.vhdl
+analyze tb2.vhdl
+elab_simulate tb2
+
+analyze tb.vhdl
+elab_simulate tb
+
+clean
+
+echo "Test successful"