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| author | Tristan Gingold <tgingold@free.fr> | 2022-08-23 06:20:33 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-08-23 06:20:33 +0200 |
| commit | e21fddad501a6da262133e220970fea42177d579 (patch) | |
| tree | d7da5c39da1555047bb8ba35c681036e87b825ae | |
| parent | 9d41b070c29508d5c941566b5687673a2e182578 (diff) | |
| download | ghdl-e21fddad501a6da262133e220970fea42177d579.tar.gz ghdl-e21fddad501a6da262133e220970fea42177d579.tar.bz2 ghdl-e21fddad501a6da262133e220970fea42177d579.zip | |
simul-vhdl_debug: disp nbr sources
| -rw-r--r-- | src/simul/simul-vhdl_debug.adb | 16 |
1 files changed, 15 insertions, 1 deletions
diff --git a/src/simul/simul-vhdl_debug.adb b/src/simul/simul-vhdl_debug.adb index 6a5b2154d..f2ce5cb67 100644 --- a/src/simul/simul-vhdl_debug.adb +++ b/src/simul/simul-vhdl_debug.adb @@ -453,6 +453,20 @@ package body Simul.Vhdl_Debug is Put_Uns32 (Uns32 (S.Collapsed_By)); New_Line; + if Boolean'(True) then + Put (" nbr sources (drv + conn):"); + New_Line; + for I in 0 .. S.Typ.W - 1 loop + Put (" "); + Put_Uns32 (I); + Put (": "); + Put_Uns32 (S.Nbr_Sources (I).Nbr_Drivers); + Put (" + "); + Put_Uns32 (S.Nbr_Sources (I).Nbr_Conns); + New_Line; + end loop; + end if; + if Opts.Value then Driver := S.Drivers; while Driver /= No_Driver_Index loop @@ -520,7 +534,7 @@ package body Simul.Vhdl_Debug is procedure Info_Signal (Idx : Signal_Index_Type) is begin - Info_Signal_Opts (Idx, (others => False)); + Info_Signal_Opts (Idx, (others => True)); end Info_Signal; -- For gdb. |