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| author | Tristan Gingold <tgingold@free.fr> | 2020-05-29 18:47:30 +0200 | 
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-05-29 18:56:32 +0200 | 
| commit | d9114d49e9509d38f329e2214b44b2dade94dacf (patch) | |
| tree | 89c565c02fe0a651a945630abce77c0ad0d7bffe | |
| parent | 26a94c92410720f9ad3cdb2f163f3b8cca3a326d (diff) | |
| download | ghdl-d9114d49e9509d38f329e2214b44b2dade94dacf.tar.gz ghdl-d9114d49e9509d38f329e2214b44b2dade94dacf.tar.bz2 ghdl-d9114d49e9509d38f329e2214b44b2dade94dacf.zip  | |
testsuite/synth: add a test for #1345
| -rw-r--r-- | testsuite/synth/issue1345/issue.vhdl | 93 | ||||
| -rwxr-xr-x | testsuite/synth/issue1345/testsuite.sh | 9 | 
2 files changed, 102 insertions, 0 deletions
diff --git a/testsuite/synth/issue1345/issue.vhdl b/testsuite/synth/issue1345/issue.vhdl new file mode 100644 index 000000000..dba178682 --- /dev/null +++ b/testsuite/synth/issue1345/issue.vhdl @@ -0,0 +1,93 @@ +library ieee; +  use ieee.std_logic_1164.all; + + +entity sequencer is +  generic ( +    seq : string +  ); +  port ( +    clk  : in  std_logic; +    data : out std_logic +  ); +end entity sequencer; + + +architecture rtl of sequencer is + +  signal index : natural := seq'low; + +  function to_bit (a : in character) return std_logic is +    variable ret : std_logic; +  begin +    case a is +      when '0' | '_' => ret := '0'; +      when '1' | '-' => ret := '1'; +      when others    => ret := 'X'; +    end case; +    return ret; +  end function to_bit; + +begin + +  process (clk) is +  begin +    if rising_edge(clk) then +      if (index < seq'high) then +        index <= index + 1; +      end if; +    end if; +  end process; + +  data <= to_bit(seq(index)); + +end architecture rtl; + + +library ieee; +  use ieee.std_logic_1164.all; + + +library ieee; +  use ieee.std_logic_1164.all; +  use ieee.numeric_std.all; + + +entity issue is +  port ( +    clk : in std_logic +  ); +end entity issue; + + +architecture psl of issue is + +  component sequencer is +    generic ( +      seq : string +    ); +    port ( +      clk  : in  std_logic; +      data : out std_logic +    ); +  end component sequencer; + +  signal a, b : std_logic; + +begin + + +  --                              0123456789012345 +  SEQ_A : sequencer generic map ("__-__-____-_____") port map (clk, a); +  SEQ_B : sequencer generic map ("_______-______-_") port map (clk, b); + + +  -- All is sensitive to rising edge of clk +  default clock is rising_edge(clk); + +  -- This assertion holds +  -- This assertion leads to a GHDL synthesis crash with bug report +  EVENTUALLY_a : assert always (a -> eventually! b); + + +end architecture psl; diff --git a/testsuite/synth/issue1345/testsuite.sh b/testsuite/synth/issue1345/testsuite.sh new file mode 100755 index 000000000..b6f83c214 --- /dev/null +++ b/testsuite/synth/issue1345/testsuite.sh @@ -0,0 +1,9 @@ +#! /bin/sh + +. ../../testenv.sh + +GHDL_STD_FLAGS=--std=08 +synth_analyze issue +clean + +echo "Test successful"  | 
