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| author | Tristan Gingold <tgingold@free.fr> | 2023-01-07 13:40:13 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2023-01-09 06:40:12 +0100 |
| commit | d85cb9909f6bf425cf444341fbea7d8b02c9334b (patch) | |
| tree | e390132d81b1421bf9c9d4351b8214ca1a6ab075 | |
| parent | 2bdb325cc263b2d0ee4f7147cf168c0b0058d0f2 (diff) | |
| download | ghdl-d85cb9909f6bf425cf444341fbea7d8b02c9334b.tar.gz ghdl-d85cb9909f6bf425cf444341fbea7d8b02c9334b.tar.bz2 ghdl-d85cb9909f6bf425cf444341fbea7d8b02c9334b.zip | |
simul: improve error recovery during elaboration
| -rw-r--r-- | src/simul/simul-vhdl_elab.adb | 15 |
1 files changed, 12 insertions, 3 deletions
diff --git a/src/simul/simul-vhdl_elab.adb b/src/simul/simul-vhdl_elab.adb index 77f3bc0b3..95c144473 100644 --- a/src/simul/simul-vhdl_elab.adb +++ b/src/simul/simul-vhdl_elab.adb @@ -188,9 +188,15 @@ package body Simul.Vhdl_Elab is Mark_Expr_Pool (Marker); Synth.Vhdl_Stmts.Synth_Assignment_Prefix (Inst, Name, Base, Typ, Off); - Res := (Base => Base.Val.S, - Typ => Unshare (Typ, Global_Pool'Access), - Offs => Off); + if Base = No_Valtyp then + Res := (Base => No_Signal_Index, + Typ => null, + Offs => No_Value_Offsets); + else + Res := (Base => Base.Val.S, + Typ => Unshare (Typ, Global_Pool'Access), + Offs => Off); + end if; Release_Expr_Pool (Marker); return Res; @@ -565,6 +571,9 @@ package body Simul.Vhdl_Elab is exit when El = Null_Node; Sig := Compute_Sub_Signal (Inst, El); + -- Exit now in case of error. + exit when Sig.Base = No_Signal_Index; + Sensitivity_Table.Append ((Sig => Sig, Prev_Sig => Signals_Table.Table (Sig.Base).Sensitivity, |