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author | Tristan Gingold <tgingold@free.fr> | 2020-03-11 18:42:01 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2020-03-11 18:42:01 +0100 |
commit | cae204093418e82299b93af809007aadd4cde36d (patch) | |
tree | 7370a644f30f66ce7a94df0b49c4ede8d9e1f578 | |
parent | 4c9651dfbb4aeb4bd22b1b6eb5436119f599f8e4 (diff) | |
download | ghdl-cae204093418e82299b93af809007aadd4cde36d.tar.gz ghdl-cae204093418e82299b93af809007aadd4cde36d.tar.bz2 ghdl-cae204093418e82299b93af809007aadd4cde36d.zip |
vhdl-ieee-std_logic_arith: recognize more conversions.
-rw-r--r-- | python/libghdl/thin/std_names.py | 367 | ||||
-rw-r--r-- | python/libghdl/thin/vhdl/nodes.py | 4 | ||||
-rw-r--r-- | src/std_names.adb | 1 | ||||
-rw-r--r-- | src/std_names.ads | 11 | ||||
-rw-r--r-- | src/vhdl/vhdl-ieee-std_logic_arith.adb | 8 | ||||
-rw-r--r-- | src/vhdl/vhdl-nodes.ads | 7 |
6 files changed, 209 insertions, 189 deletions
diff --git a/python/libghdl/thin/std_names.py b/python/libghdl/thin/std_names.py index 9ae16a255..b691cce86 100644 --- a/python/libghdl/thin/std_names.py +++ b/python/libghdl/thin/std_names.py @@ -604,186 +604,187 @@ class Name: Conv_Signed = 816 Conv_Unsigned = 817 Conv_Integer = 818 - Ceil = 819 - Round = 820 - Log2 = 821 - Sin = 822 - Cos = 823 - Last_Ieee_Name = 823 - First_Synthesis = 824 - Allconst = 824 - Allseq = 825 - Anyconst = 826 - Anyseq = 827 - Last_Synthesis = 827 - First_Directive = 828 - Define = 828 - Endif = 829 - Ifdef = 830 - Ifndef = 831 - Include = 832 - Timescale = 833 - Undef = 834 - Protect = 835 - Begin_Protected = 836 - End_Protected = 837 - Key_Block = 838 - Data_Block = 839 - Line = 840 - Celldefine = 841 - Endcelldefine = 842 - Default_Nettype = 843 - Resetall = 844 - Last_Directive = 844 - First_Systask = 845 - Bits = 845 - D_Root = 846 - D_Unit = 847 - Last_Systask = 847 - First_SV_Method = 848 - Size = 848 - Insert = 849 - Delete = 850 - Pop_Front = 851 - Pop_Back = 852 - Push_Front = 853 - Push_Back = 854 - Name = 855 - Len = 856 - Substr = 857 - Exists = 858 - Atoi = 859 - Itoa = 860 - Find = 861 - Find_Index = 862 - Find_First = 863 - Find_First_Index = 864 - Find_Last = 865 - Find_Last_Index = 866 - Num = 867 - Randomize = 868 - Pre_Randomize = 869 - Post_Randomize = 870 - Srandom = 871 - Get_Randstate = 872 - Set_Randstate = 873 - Seed = 874 - State = 875 - Last_SV_Method = 875 - First_BSV = 876 - uAction = 876 - uActionValue = 877 - BVI = 878 - uC = 879 - uCF = 880 - uE = 881 - uSB = 882 - uSBR = 883 - Action = 884 - Endaction = 885 - Actionvalue = 886 - Endactionvalue = 887 - Ancestor = 888 - Clocked_By = 889 - Default_Clock = 890 - Default_Reset = 891 - Dependencies = 892 - Deriving = 893 - Determines = 894 - Enable = 895 - Ifc_Inout = 896 - Input_Clock = 897 - Input_Reset = 898 - Instance = 899 - Endinstance = 900 - Let = 901 - Match = 902 - Method = 903 - Endmethod = 904 - Numeric = 905 - Output_Clock = 906 - Output_Reset = 907 - Par = 908 - Endpar = 909 - Path = 910 - Provisos = 911 - Ready = 912 - Reset_By = 913 - Rule = 914 - Endrule = 915 - Rules = 916 - Endrules = 917 - Same_Family = 918 - Schedule = 919 - Seq = 920 - Endseq = 921 - Typeclass = 922 - Endtypeclass = 923 - Valueof = 924 - uValueof = 925 - Last_BSV = 925 - First_Comment = 926 - Psl = 926 - Pragma = 927 - Synthesis = 928 - Synopsys = 929 - Translate_Off = 930 - Translate_On = 931 - Last_Comment = 931 - First_PSL = 932 - A = 932 - Af = 933 - Ag = 934 - Ax = 935 - Abort = 936 - Assume_Guarantee = 937 - Before = 938 - Clock = 939 - E = 940 - Ef = 941 - Eg = 942 - Ex = 943 - Endpoint = 944 - Eventually = 945 - Fairness = 946 - Fell = 947 - Forall = 948 - G = 949 - Inf = 950 - Inherit = 951 - Never = 952 - Next_A = 953 - Next_E = 954 - Next_Event = 955 - Next_Event_A = 956 - Next_Event_E = 957 - Prev = 958 - Rose = 959 - Strong = 960 - W = 961 - Whilenot = 962 - Within = 963 - X = 964 - Last_PSL = 964 - First_Edif = 965 - Celltype = 975 - View = 976 - Viewtype = 977 - Direction = 978 - Contents = 979 - Net = 980 - Viewref = 981 - Cellref = 982 - Libraryref = 983 - Portinstance = 984 - Joined = 985 - Portref = 986 - Instanceref = 987 - Design = 988 - Designator = 989 - Owner = 990 - Member = 991 - Number = 992 - Rename = 993 - Userdata = 994 - Last_Edif = 994 + Conv_Std_Logic_Vector = 819 + Ceil = 820 + Round = 821 + Log2 = 822 + Sin = 823 + Cos = 824 + Last_Ieee_Name = 824 + First_Synthesis = 825 + Allconst = 825 + Allseq = 826 + Anyconst = 827 + Anyseq = 828 + Last_Synthesis = 828 + First_Directive = 829 + Define = 829 + Endif = 830 + Ifdef = 831 + Ifndef = 832 + Include = 833 + Timescale = 834 + Undef = 835 + Protect = 836 + Begin_Protected = 837 + End_Protected = 838 + Key_Block = 839 + Data_Block = 840 + Line = 841 + Celldefine = 842 + Endcelldefine = 843 + Default_Nettype = 844 + Resetall = 845 + Last_Directive = 845 + First_Systask = 846 + Bits = 846 + D_Root = 847 + D_Unit = 848 + Last_Systask = 848 + First_SV_Method = 849 + Size = 849 + Insert = 850 + Delete = 851 + Pop_Front = 852 + Pop_Back = 853 + Push_Front = 854 + Push_Back = 855 + Name = 856 + Len = 857 + Substr = 858 + Exists = 859 + Atoi = 860 + Itoa = 861 + Find = 862 + Find_Index = 863 + Find_First = 864 + Find_First_Index = 865 + Find_Last = 866 + Find_Last_Index = 867 + Num = 868 + Randomize = 869 + Pre_Randomize = 870 + Post_Randomize = 871 + Srandom = 872 + Get_Randstate = 873 + Set_Randstate = 874 + Seed = 875 + State = 876 + Last_SV_Method = 876 + First_BSV = 877 + uAction = 877 + uActionValue = 878 + BVI = 879 + uC = 880 + uCF = 881 + uE = 882 + uSB = 883 + uSBR = 884 + Action = 885 + Endaction = 886 + Actionvalue = 887 + Endactionvalue = 888 + Ancestor = 889 + Clocked_By = 890 + Default_Clock = 891 + Default_Reset = 892 + Dependencies = 893 + Deriving = 894 + Determines = 895 + Enable = 896 + Ifc_Inout = 897 + Input_Clock = 898 + Input_Reset = 899 + Instance = 900 + Endinstance = 901 + Let = 902 + Match = 903 + Method = 904 + Endmethod = 905 + Numeric = 906 + Output_Clock = 907 + Output_Reset = 908 + Par = 909 + Endpar = 910 + Path = 911 + Provisos = 912 + Ready = 913 + Reset_By = 914 + Rule = 915 + Endrule = 916 + Rules = 917 + Endrules = 918 + Same_Family = 919 + Schedule = 920 + Seq = 921 + Endseq = 922 + Typeclass = 923 + Endtypeclass = 924 + Valueof = 925 + uValueof = 926 + Last_BSV = 926 + First_Comment = 927 + Psl = 927 + Pragma = 928 + Synthesis = 929 + Synopsys = 930 + Translate_Off = 931 + Translate_On = 932 + Last_Comment = 932 + First_PSL = 933 + A = 933 + Af = 934 + Ag = 935 + Ax = 936 + Abort = 937 + Assume_Guarantee = 938 + Before = 939 + Clock = 940 + E = 941 + Ef = 942 + Eg = 943 + Ex = 944 + Endpoint = 945 + Eventually = 946 + Fairness = 947 + Fell = 948 + Forall = 949 + G = 950 + Inf = 951 + Inherit = 952 + Never = 953 + Next_A = 954 + Next_E = 955 + Next_Event = 956 + Next_Event_A = 957 + Next_Event_E = 958 + Prev = 959 + Rose = 960 + Strong = 961 + W = 962 + Whilenot = 963 + Within = 964 + X = 965 + Last_PSL = 965 + First_Edif = 966 + Celltype = 976 + View = 977 + Viewtype = 978 + Direction = 979 + Contents = 980 + Net = 981 + Viewref = 982 + Cellref = 983 + Libraryref = 984 + Portinstance = 985 + Joined = 986 + Portref = 987 + Instanceref = 988 + Design = 989 + Designator = 990 + Owner = 991 + Member = 992 + Number = 993 + Rename = 994 + Userdata = 995 + Last_Edif = 995 diff --git a/python/libghdl/thin/vhdl/nodes.py b/python/libghdl/thin/vhdl/nodes.py index 28ff681ca..2da9debfd 100644 --- a/python/libghdl/thin/vhdl/nodes.py +++ b/python/libghdl/thin/vhdl/nodes.py @@ -1405,6 +1405,10 @@ class Iir_Predefined: Ieee_Std_Logic_Arith_Conv_Integer_Uns = 422 Ieee_Std_Logic_Arith_Conv_Integer_Sgn = 423 Ieee_Std_Logic_Arith_Conv_Integer_Log = 424 + Ieee_Std_Logic_Arith_Conv_Vector_Int = 425 + Ieee_Std_Logic_Arith_Conv_Vector_Uns = 426 + Ieee_Std_Logic_Arith_Conv_Vector_Sgn = 427 + Ieee_Std_Logic_Arith_Conv_Vector_Log = 428 Get_Kind = libghdl.vhdl__nodes__get_kind Get_Location = libghdl.vhdl__nodes__get_location diff --git a/src/std_names.adb b/src/std_names.adb index 1a7de9a6a..2511c779c 100644 --- a/src/std_names.adb +++ b/src/std_names.adb @@ -655,6 +655,7 @@ package body Std_Names is Def ("conv_signed", Name_Conv_Signed); Def ("conv_unsigned", Name_Conv_Unsigned); Def ("conv_integer", Name_Conv_Integer); + Def ("conv_std_logic_vector", Name_Conv_Std_Logic_Vector); Def ("ceil", Name_Ceil); Def ("round", Name_Round); Def ("log2", Name_Log2); diff --git a/src/std_names.ads b/src/std_names.ads index d6c7621c6..5b54d14e4 100644 --- a/src/std_names.ads +++ b/src/std_names.ads @@ -738,11 +738,12 @@ package Std_Names is Name_Conv_Signed : constant Name_Id := Name_First_Ieee_Name + 025; Name_Conv_Unsigned : constant Name_Id := Name_First_Ieee_Name + 026; Name_Conv_Integer : constant Name_Id := Name_First_Ieee_Name + 027; - Name_Ceil : constant Name_Id := Name_First_Ieee_Name + 028; - Name_Round : constant Name_Id := Name_First_Ieee_Name + 029; - Name_Log2 : constant Name_Id := Name_First_Ieee_Name + 030; - Name_Sin : constant Name_Id := Name_First_Ieee_Name + 031; - Name_Cos : constant Name_Id := Name_First_Ieee_Name + 032; + Name_Conv_Std_Logic_Vector : constant Name_Id := Name_First_Ieee_Name + 028; + Name_Ceil : constant Name_Id := Name_First_Ieee_Name + 029; + Name_Round : constant Name_Id := Name_First_Ieee_Name + 030; + Name_Log2 : constant Name_Id := Name_First_Ieee_Name + 031; + Name_Sin : constant Name_Id := Name_First_Ieee_Name + 032; + Name_Cos : constant Name_Id := Name_First_Ieee_Name + 033; Name_Last_Ieee_Name : constant Name_Id := Name_Cos; Name_First_Synthesis : constant Name_Id := Name_Last_Ieee_Name + 1; diff --git a/src/vhdl/vhdl-ieee-std_logic_arith.adb b/src/vhdl/vhdl-ieee-std_logic_arith.adb index 28bf913a1..e8a7fbd1b 100644 --- a/src/vhdl/vhdl-ieee-std_logic_arith.adb +++ b/src/vhdl/vhdl-ieee-std_logic_arith.adb @@ -45,6 +45,12 @@ package body Vhdl.Ieee.Std_Logic_Arith is Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Integer_Int, Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Integer_Log); + Conv_Vec_Patterns : constant Conv_Pattern_Type := + (Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Vector_Sgn, + Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Vector_Uns, + Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Vector_Int, + Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Vector_Log); + Error : exception; procedure Extract_Declarations (Pkg : Iir_Package_Declaration) @@ -152,6 +158,8 @@ package body Vhdl.Ieee.Std_Logic_Arith is case Get_Identifier (Decl) is when Name_Conv_Unsigned => Def := Handle_Conv (Conv_Uns_Patterns); + when Name_Conv_Std_Logic_Vector => + Def := Handle_Conv (Conv_Vec_Patterns); when others => null; end case; diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index 54fba3db2..ed83cd157 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -5746,7 +5746,12 @@ package Vhdl.Nodes is Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Integer_Int, Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Integer_Uns, Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Integer_Sgn, - Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Integer_Log + Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Integer_Log, + + Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Vector_Int, + Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Vector_Uns, + Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Vector_Sgn, + Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Vector_Log ); -- Return TRUE iff FUNC is a short-cut predefined function. |