synth: adjust output for dyn_insert, add dpram2 test.

4 files changed, 67 insertions, 3 deletions

diff --git a/src/synth/netlists-disp_vhdl.adb b/src/synth/netlists-disp_vhdl.adb
index 95d01102a..800fc585c 100644
--- a/src/synth/netlists-disp_vhdl.adb
+++ b/src/synth/netlists-disp_vhdl.adb
@@ -571,8 +571,8 @@ package body Netlists.Disp_Vhdl is
                   "  begin" & NL &
                   "    \o0 <= \i0;" & NL &
                   "    \o0 (" &
-                  "to_integer (signed (\i2)) * \p0 + (\sp1 + \n0)" & NL &
-                  "         downto to_integer (signed (\i2)) * \p0 + (\sp1))" &
+                  "to_integer (\ui2) * \p0 + (\sp1 + \n0)" & NL &
+                  "        downto to_integer (\ui2) * \p0 + (\sp1))" &
                   " <= \i1;" & NL &
                   "  end process;" & NL,
                   Inst, (0 => Iw - 1));
diff --git a/testsuite/synth/arr02/dpram2.vhdl b/testsuite/synth/arr02/dpram2.vhdl
new file mode 100644
index 000000000..c21a0ee78
--- /dev/null
+++ b/testsuite/synth/arr02/dpram2.vhdl
@@ -0,0 +1,24 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity dpram2 is
+  port (raddr : std_logic_vector (3 downto 0);
+        rdat : out std_logic_vector (7 downto 0);
+        waddr : std_logic_vector (3 downto 0);
+        wdat : std_logic_vector (7 downto 0);
+        clk : std_logic);
+end dpram2;
+
+architecture behav of dpram2 is
+begin
+  process (clk)
+    type memtype is array (15 downto 0) of std_logic_vector (7 downto 0);
+    variable mem : memtype;
+  begin
+    if rising_edge (clk) then
+      rdat <= mem (to_integer(unsigned (raddr)));
+      mem (to_integer(unsigned (waddr))) := wdat;
+    end if;
+  end process;
+end behav;
diff --git a/testsuite/synth/arr02/tb_dpram2.vhdl b/testsuite/synth/arr02/tb_dpram2.vhdl
new file mode 100644
index 000000000..f66363345
--- /dev/null
+++ b/testsuite/synth/arr02/tb_dpram2.vhdl
@@ -0,0 +1,40 @@
+entity tb_dpram2 is
+end tb_dpram2;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_dpram2 is
+  signal raddr : std_logic_vector(3 downto 0);
+  signal rdat : std_logic_vector(7 downto 0);
+  signal waddr : std_logic_vector(3 downto 0);
+  signal wdat : std_logic_vector(7 downto 0);
+  signal clk : std_logic;
+begin
+  dut: entity work.dpram2
+    port map (raddr => raddr, rdat => rdat, waddr => waddr, wdat => wdat,
+              clk => clk);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    raddr <= "0000";
+    waddr <= x"a";
+    wdat <= x"5a";
+    pulse;
+
+    raddr <= x"a";
+    waddr <= x"7";
+    wdat <= x"87";
+    pulse;
+    assert rdat = x"5a" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/arr02/testsuite.sh b/testsuite/synth/arr02/testsuite.sh
index f11c3aa42..6dd2fb477 100755
--- a/testsuite/synth/arr02/testsuite.sh
+++ b/testsuite/synth/arr02/testsuite.sh
@@ -2,7 +2,7 @@
 
 . ../../testenv.sh
 
-for t in rom1 dpram1; do
+for t in rom1 dpram1 dpram2; do
     analyze $t.vhdl tb_$t.vhdl
     elab_simulate tb_$t
     clean