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author | Tristan Gingold <tgingold@free.fr> | 2016-10-17 21:10:05 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2016-10-17 21:10:05 +0200 |
commit | b42b707e1f1977abe82d0d6a8ecce5fbee38faa8 (patch) | |
tree | 6ed895b3f77f777b64967a8604fbecd5832688be | |
parent | 5e2a4e1c07e1f2e930847afc6e2c5924c8393ac7 (diff) | |
download | ghdl-b42b707e1f1977abe82d0d6a8ecce5fbee38faa8.tar.gz ghdl-b42b707e1f1977abe82d0d6a8ecce5fbee38faa8.tar.bz2 ghdl-b42b707e1f1977abe82d0d6a8ecce5fbee38faa8.zip |
Add testcase for --file-to-xml
-rw-r--r-- | testsuite/gna/bug062/ex.vhdl | 20 | ||||
-rwxr-xr-x | testsuite/gna/bug062/testsuite.sh | 9 |
2 files changed, 29 insertions, 0 deletions
diff --git a/testsuite/gna/bug062/ex.vhdl b/testsuite/gna/bug062/ex.vhdl new file mode 100644 index 000000000..9a63931f2 --- /dev/null +++ b/testsuite/gna/bug062/ex.vhdl @@ -0,0 +1,20 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity ex is + port (clk, en : std_ulogic; + r1: std_ulogic; + r0: out std_ulogic); +end ex; + +architecture behav of ex is +begin + process(clk) + begin + if rising_edge(clk) then + if en = '1' then + r0 <= r1; + end if; + end if; + end process; +end behav; diff --git a/testsuite/gna/bug062/testsuite.sh b/testsuite/gna/bug062/testsuite.sh new file mode 100755 index 000000000..ce437caa3 --- /dev/null +++ b/testsuite/gna/bug062/testsuite.sh @@ -0,0 +1,9 @@ +#! /bin/sh + +. ../../testenv.sh + +$GHDL --file-to-xml ex.vhdl > ex.xml + +rm -f ex.xml + +echo "Test successful" |