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author | Tristan Gingold <tgingold@free.fr> | 2019-01-04 07:48:34 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-01-04 13:21:17 +0100 |
commit | b054bf21a3a9aed8c9756c60ce8209cc800c104b (patch) | |
tree | caf032bc888805e8c96a8949563a74cb499a64b9 | |
parent | 21a6d28f8f06b7491143f14931574160101a2699 (diff) | |
download | ghdl-b054bf21a3a9aed8c9756c60ce8209cc800c104b.tar.gz ghdl-b054bf21a3a9aed8c9756c60ce8209cc800c104b.tar.bz2 ghdl-b054bf21a3a9aed8c9756c60ce8209cc800c104b.zip |
Adjust testcase.
-rw-r--r-- | testsuite/gna/issue339/test_bench.vhdl | 2 | ||||
-rwxr-xr-x | testsuite/gna/issue339/testsuite.sh | 9 |
2 files changed, 9 insertions, 2 deletions
diff --git a/testsuite/gna/issue339/test_bench.vhdl b/testsuite/gna/issue339/test_bench.vhdl index 74344dac7..74d58e274 100644 --- a/testsuite/gna/issue339/test_bench.vhdl +++ b/testsuite/gna/issue339/test_bench.vhdl @@ -22,7 +22,7 @@ architecture bench of test_bench is signal s_clk : std_logic := '1';
begin
- s_rst <= '1' after 50 ns;
+ s_rst <= '0' after 50 ns;
s_clk <= not s_clk after 10 ns;
write_result : process (s_rst, s_clk) is
diff --git a/testsuite/gna/issue339/testsuite.sh b/testsuite/gna/issue339/testsuite.sh index 8d02ad161..8a172d20b 100755 --- a/testsuite/gna/issue339/testsuite.sh +++ b/testsuite/gna/issue339/testsuite.sh @@ -4,8 +4,15 @@ export GHDL_STD_FLAGS=--std=08 analyze test_pkg.vhdl test_bench.vhdl -elab_simulate test_bench --stop-time=700ns +elab test_bench +if false && ghdl_has_feature test_bench ghw; then + simulate test_bench --stop-time=700ns --wave=w.ghw +else + simulate test_bench --stop-time=700ns +fi clean +rm -f w.ghw +rm -f output.txt echo "Test successful" |