diff options
author | Tristan Gingold <tgingold@free.fr> | 2022-08-13 06:52:16 +0200 |
---|---|---|
committer | Tristan Gingold <tgingold@free.fr> | 2022-08-14 20:51:01 +0200 |
commit | ad0ca9a8da328463c29a59c9f3832848a3ea65ed (patch) | |
tree | bf8da0cbda965936fb15c690047c19ae800031b7 | |
parent | 550c8e653ab6c5ff6581d0b08c0449bede55557f (diff) | |
download | ghdl-ad0ca9a8da328463c29a59c9f3832848a3ea65ed.tar.gz ghdl-ad0ca9a8da328463c29a59c9f3832848a3ea65ed.tar.bz2 ghdl-ad0ca9a8da328463c29a59c9f3832848a3ea65ed.zip |
testsuite/synth: add tests for #2077
-rw-r--r-- | testsuite/synth/issue2077/ent6.vhdl | 37 | ||||
-rw-r--r-- | testsuite/synth/issue2077/tb_ent6.vhdl | 49 |
2 files changed, 86 insertions, 0 deletions
diff --git a/testsuite/synth/issue2077/ent6.vhdl b/testsuite/synth/issue2077/ent6.vhdl new file mode 100644 index 000000000..07ffb3653 --- /dev/null +++ b/testsuite/synth/issue2077/ent6.vhdl @@ -0,0 +1,37 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity ent6 is + generic ( + WIDTH : positive := 8; + DEPTH : positive := 256 + ); + port ( + clk: in std_logic; + + write_enable: in std_logic; + write_address: in natural range 0 to DEPTH-1; + input: in std_logic_vector(WIDTH-1 downto 0); + + read_address: in natural range 0 to DEPTH-1; + output: out std_logic + ); +end entity; + +architecture a of ent6 is +begin + process(clk) + type memory_t is array(0 to DEPTH-1) of std_logic_vector(WIDTH-1 downto 0); + + variable memories : memory_t; + begin + if rising_edge(clk) then + output <= and memories(read_address); + + if write_enable then + memories(write_address) := input; + end if; + end if; + end process; +end architecture; diff --git a/testsuite/synth/issue2077/tb_ent6.vhdl b/testsuite/synth/issue2077/tb_ent6.vhdl new file mode 100644 index 000000000..186f46a01 --- /dev/null +++ b/testsuite/synth/issue2077/tb_ent6.vhdl @@ -0,0 +1,49 @@ +entity tb_ent6 is +end tb_ent6; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_ent6 is + signal waddr2, raddr2 : natural range 0 to 255; + signal wdat : std_logic_vector (7 downto 0); + signal rdat : std_logic; + signal wen : std_logic; + signal clk : std_logic; +begin + dut: entity work.ent6 + generic map (WIDTH => 8) + port map (clk => clk, write_enable => wen, + write_address => waddr2, input => wdat, + read_address => raddr2, output => rdat); + + process + procedure pulse is + begin + clk <= '0'; + wait for 1 ns; + clk <= '1'; + wait for 1 ns; + end pulse; + begin + waddr2 <= 3; + wdat <= x"13"; + wen <= '1'; + pulse; + + waddr2 <= 2; + wdat <= x"ff"; + pulse; + + raddr2 <= 3; + wen <= '0'; + pulse; + assert rdat = '0' severity failure; + + raddr2 <= 2; + pulse; + assert rdat = '1' severity failure; + + wait; + end process; +end behav; |