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author | Tristan Gingold <tgingold@free.fr> | 2021-03-29 20:36:01 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2021-03-29 21:25:07 +0200 |
commit | 9f58adc16cb9306b5bf45cfaa5c7167bc52a56f8 (patch) | |
tree | cd26aabc6d7648b16cbe519215d63d5d1576abe2 | |
parent | 9ab4fd1819f8f99f3ad71727f4ebf013657d6db5 (diff) | |
download | ghdl-9f58adc16cb9306b5bf45cfaa5c7167bc52a56f8.tar.gz ghdl-9f58adc16cb9306b5bf45cfaa5c7167bc52a56f8.tar.bz2 ghdl-9f58adc16cb9306b5bf45cfaa5c7167bc52a56f8.zip |
ghdlsynth: add --out=raw-vhdl. For #1702
-rw-r--r-- | src/ghdldrv/ghdlsynth.adb | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/src/ghdldrv/ghdlsynth.adb b/src/ghdldrv/ghdlsynth.adb index ffb3fb10d..c3101fc16 100644 --- a/src/ghdldrv/ghdlsynth.adb +++ b/src/ghdldrv/ghdlsynth.adb @@ -55,7 +55,7 @@ package body Ghdlsynth is type Out_Format is (Format_Default, Format_Raw, Format_Dump, Format_Dot, - Format_Vhdl, + Format_Vhdl, Format_Raw_Vhdl, Format_None); type Name_Id_Array is array (Natural range <>) of Name_Id; @@ -201,6 +201,8 @@ package body Ghdlsynth is Cmd.Oformat := Format_None; elsif Option = "--out=vhdl" then Cmd.Oformat := Format_Vhdl; + elsif Option = "--out=raw-vhdl" then + Cmd.Oformat := Format_Raw_Vhdl; elsif Option = "-di" then Flag_Debug_Noinference := True; elsif Option = "-dc" then @@ -419,12 +421,10 @@ package body Ghdlsynth is when Format_Dot => Netlists.Disp_Dot.Disp_Dot_Top_Module (Res); when Format_Vhdl => - if Boolean'(True) then - Ent := Vhdl.Utils.Get_Entity_From_Configuration (Config); - Synth.Disp_Vhdl.Disp_Vhdl_Wrapper (Ent, Res, Inst); - else - Netlists.Disp_Vhdl.Disp_Vhdl (Res); - end if; + Ent := Vhdl.Utils.Get_Entity_From_Configuration (Config); + Synth.Disp_Vhdl.Disp_Vhdl_Wrapper (Ent, Res, Inst); + when Format_Raw_Vhdl => + Netlists.Disp_Vhdl.Disp_Vhdl (Res); end case; end Disp_Design; |