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| author | Tristan Gingold <tgingold@free.fr> | 2020-09-20 08:44:17 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-09-20 08:47:50 +0200 |
| commit | 9b1e128e8cac7f8cf5259f409b9b2c024cf457bf (patch) | |
| tree | ef9697c86b87385f8bf7ef184c14628a1f94fddd | |
| parent | 81150cf4c2bda2665a82a4cb98f81a21ecd6d4c6 (diff) | |
| download | ghdl-9b1e128e8cac7f8cf5259f409b9b2c024cf457bf.tar.gz ghdl-9b1e128e8cac7f8cf5259f409b9b2c024cf457bf.tar.bz2 ghdl-9b1e128e8cac7f8cf5259f409b9b2c024cf457bf.zip | |
synth-disp_vhdl: extend vector conversions (for any range). For #1460
| -rw-r--r-- | src/synth/synth-disp_vhdl.adb | 22 |
1 files changed, 20 insertions, 2 deletions
diff --git a/src/synth/synth-disp_vhdl.adb b/src/synth/synth-disp_vhdl.adb index e9e99fa6f..4fb144e12 100644 --- a/src/synth/synth-disp_vhdl.adb +++ b/src/synth/synth-disp_vhdl.adb @@ -37,10 +37,22 @@ with Synth.Objtypes; use Synth.Objtypes; package body Synth.Disp_Vhdl is procedure Disp_Signal (Desc : Port_Desc) is begin + if Desc.W > 1 then + Put (" subtype typ"); + Put_Name (Desc.Name); + Put (" is "); + Put_Type (Desc.W); + Put_Line (";"); + end if; Put (" signal "); Put_Name (Desc.Name); Put (": "); - Put_Type (Desc.W); + if Desc.W > 1 then + Put ("typ"); + Put_Name (Desc.Name); + else + Put_Type (Desc.W); + end if; Put_Line (";"); end Disp_Signal; @@ -160,7 +172,13 @@ package body Synth.Disp_Vhdl is W := Typ.Vbound.Len; Disp_In_Lhs (Mname, Off, W, Full); if W > 1 then - Put ("std_logic_vector("); + if Full then + Put ("typwrap_"); + Put (Mname); + else + Put ("std_logic_vector"); + end if; + Put ("("); end if; Put (Pfx); if W = 1 then |