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author | Tristan Gingold <tgingold@free.fr> | 2020-03-13 19:21:04 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2020-03-13 19:21:04 +0100 |
commit | 8b0a0ce1738beda9b7288a3d7df19cbbe82b7d23 (patch) | |
tree | 7f796da78d465cf5cea6ac32cb6b4a6314def73d | |
parent | a13ef8cc10b50432300f2d376bcfa8fff24351b7 (diff) | |
download | ghdl-8b0a0ce1738beda9b7288a3d7df19cbbe82b7d23.tar.gz ghdl-8b0a0ce1738beda9b7288a3d7df19cbbe82b7d23.tar.bz2 ghdl-8b0a0ce1738beda9b7288a3d7df19cbbe82b7d23.zip |
testsuite/synth: add a test.
-rw-r--r-- | testsuite/synth/const01/const02.vhdl | 65 |
1 files changed, 65 insertions, 0 deletions
diff --git a/testsuite/synth/const01/const02.vhdl b/testsuite/synth/const01/const02.vhdl new file mode 100644 index 000000000..cf82c928d --- /dev/null +++ b/testsuite/synth/const01/const02.vhdl @@ -0,0 +1,65 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity const02a is + generic (init : std_logic_vector(31 downto 0) := x"10203040"); + port (o : out std_logic_vector(0 to 31)); +end const02a; + +architecture behav of const02a is + type slv_array is array (natural range <>) of std_logic_vector(7 downto 0); + + function conv (v : std_logic_vector) return slv_array is + variable r : slv_array(0 to v'length / 8 - 1); + begin + for i in 0 to r'length-1 loop + r (i) := v(v'length - (i*8) - 1 downto v'length - (i*8) - 8); + end loop; + return r; + end conv; + + constant res : slv_array (0 to 3) := conv (init); +begin + o (0 to 7) <= res (0); + o (8 to 15) <= res (1); + o (16 to 23) <= res (2); + o (24 to 31) <= res (3); +end behav; + +library ieee; +use ieee.std_logic_1164.all; + +entity const02b is + generic (init : std_logic_vector(31 downto 0)); + port (o : out std_logic_vector(0 to 31)); +end const02b; + +architecture behav of const02b is +begin + inst: entity work.const02a + generic map (init => init) + port map (o => o); +end behav; + + +library ieee; +use ieee.std_logic_1164.all; + +package cst_pkg is + constant init : std_logic_vector(31 downto 0) := x"10203040"; +end cst_pkg; + +library ieee; +use ieee.std_logic_1164.all; +use work.cst_pkg.all; + +entity const02 is + port (o : out std_logic_vector(0 to 31)); +end const02; + +architecture behav of const02 is +begin + inst: entity work.const02b + generic map (init => init) + port map (o => o); +end behav; |