Formatting by black.

4 files changed, 24 insertions, 6 deletions

diff --git a/pyGHDL/dom/Concurrent.py b/pyGHDL/dom/Concurrent.py
index 0435792ef..8dcec9bdb 100644
--- a/pyGHDL/dom/Concurrent.py
+++ b/pyGHDL/dom/Concurrent.py
@@ -35,7 +35,12 @@ from typing import Iterable
 from pyTooling.Decorators import export
 
 from pyGHDL.dom.Range import Range
-from pyGHDL.dom.Symbol import ArchitectureSymbol, EntityInstantiationSymbol, ComponentInstantiationSymbol, ConfigurationInstantiationSymbol
+from pyGHDL.dom.Symbol import (
+    ArchitectureSymbol,
+    EntityInstantiationSymbol,
+    ComponentInstantiationSymbol,
+    ConfigurationInstantiationSymbol,
+)
 from pyVHDLModel.SyntaxModel import (
     GenericAssociationItem as VHDLModel_GenericAssociationItem,
     PortAssociationItem as VHDLModel_PortAssociationItem,
@@ -71,7 +76,12 @@ from pyVHDLModel.SyntaxModel import (
 from pyGHDL.libghdl import Iir, utils
 from pyGHDL.libghdl.vhdl import nodes
 from pyGHDL.dom import DOMMixin, DOMException, Position
-from pyGHDL.dom._Utils import GetNameOfNode, GetEntityInstantiationSymbol, GetComponentInstantiationSymbol, GetConfigurationInstantiationSymbol
+from pyGHDL.dom._Utils import (
+    GetNameOfNode,
+    GetEntityInstantiationSymbol,
+    GetComponentInstantiationSymbol,
+    GetConfigurationInstantiationSymbol,
+)
 
 
 @export
@@ -126,7 +136,7 @@ class EntityInstantiation(VHDLModel_EntityInstantiation, DOMMixin):
         instantiationNode: Iir,
         label: str,
         entitySymbol: EntityInstantiationSymbol,
-        architectureSymbol: ArchitectureSymbol = None,   # TODO: merge both symbols ?
+        architectureSymbol: ArchitectureSymbol = None,  # TODO: merge both symbols ?
         genericAssociations: Iterable[AssociationItem] = None,
         portAssociations: Iterable[AssociationItem] = None,
     ):
diff --git a/pyGHDL/dom/DesignUnit.py b/pyGHDL/dom/DesignUnit.py
index 28a5dc0b6..881a7f2eb 100644
--- a/pyGHDL/dom/DesignUnit.py
+++ b/pyGHDL/dom/DesignUnit.py
@@ -48,7 +48,8 @@ from pyVHDLModel import (
     LibraryClause as VHDLModel_LibraryClause,
     UseClause as VHDLModel_UseClause,
     ContextReference as VHDLModel_ContextReference,
-    Name, ContextUnion,
+    Name,
+    ContextUnion,
 )
 from pyVHDLModel.SyntaxModel import (
     Entity as VHDLModel_Entity,
diff --git a/pyGHDL/dom/Symbol.py b/pyGHDL/dom/Symbol.py
index a9b919ccb..76f794650 100644
--- a/pyGHDL/dom/Symbol.py
+++ b/pyGHDL/dom/Symbol.py
@@ -146,9 +146,11 @@ class PackageSymbol(VHDLModel_PackageSymbol, DOMMixin):
         super().__init__(identifier)
         DOMMixin.__init__(self, identifierNode)
 
+
 # TODO: ||||                 ||||
 # TODO: VVVV   old symbols   VVVV
 
+
 @export
 class SimpleSubtypeSymbol(VHDLModel_SimpleSubtypeSymbol, DOMMixin):
     def __init__(self, node: Iir, subtypeName: Name):
diff --git a/pyGHDL/dom/_Utils.py b/pyGHDL/dom/_Utils.py
index bc1841990..09f336c03 100644
--- a/pyGHDL/dom/_Utils.py
+++ b/pyGHDL/dom/_Utils.py
@@ -39,7 +39,10 @@ from pyGHDL.dom.Symbol import (
     PackageReferenceSymbol,
     PackageMembersReferenceSymbol,
     AllPackageMembersReferenceSymbol,
-    ContextReferenceSymbol, EntityInstantiationSymbol, ComponentInstantiationSymbol, ConfigurationInstantiationSymbol,
+    ContextReferenceSymbol,
+    EntityInstantiationSymbol,
+    ComponentInstantiationSymbol,
+    ConfigurationInstantiationSymbol,
 )
 from pyVHDLModel.SyntaxModel import Mode
 
@@ -166,7 +169,9 @@ def GetPackageSymbol(node: Iir) -> PackageReferenceSymbol:
         raise DOMException(f"{kind.name} at {Position.parse(node)}")
 
 
-def GetPackageMemberSymbol(node: Iir) -> Union[PackageReferenceSymbol, PackageMembersReferenceSymbol, AllPackageMembersReferenceSymbol]:
+def GetPackageMemberSymbol(
+    node: Iir,
+) -> Union[PackageReferenceSymbol, PackageMembersReferenceSymbol, AllPackageMembersReferenceSymbol]:
     kind = GetIirKindOfNode(node)
     prefixName = GetPackageSymbol(nodes.Get_Prefix(node))
     if kind == nodes.Iir_Kind.Selected_Name: