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| author | Tristan Gingold <tgingold@free.fr> | 2022-05-30 04:12:34 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-05-30 04:12:34 +0200 |
| commit | 7fc2f111d011a82e9a4a7b5aba698e5ccffec871 (patch) | |
| tree | b3f4a9e18c0a45de12d3575754e86c577750fe89 | |
| parent | c36104e1e61f07732a6fe77edec3b51f044b9dfe (diff) | |
| download | ghdl-7fc2f111d011a82e9a4a7b5aba698e5ccffec871.tar.gz ghdl-7fc2f111d011a82e9a4a7b5aba698e5ccffec871.tar.bz2 ghdl-7fc2f111d011a82e9a4a7b5aba698e5ccffec871.zip | |
synth-vhdl_oper: add hooks for bit edge
| -rw-r--r-- | src/synth/synth-vhdl_oper.adb | 12 | ||||
| -rw-r--r-- | src/synth/synth-vhdl_oper.ads | 3 |
2 files changed, 15 insertions, 0 deletions
diff --git a/src/synth/synth-vhdl_oper.adb b/src/synth/synth-vhdl_oper.adb index 0f25e63da..7c589b993 100644 --- a/src/synth/synth-vhdl_oper.adb +++ b/src/synth/synth-vhdl_oper.adb @@ -1917,6 +1917,18 @@ package body Synth.Vhdl_Oper is return Synth_Minmax (Ctxt, L, R, Res_Typ, Id_Slt, Expr); when Iir_Predefined_Integer_Maximum => return Synth_Minmax (Ctxt, L, R, Res_Typ, Id_Sgt, Expr); + when Iir_Predefined_Bit_Rising_Edge => + if Hook_Bit_Rising_Edge /= null then + return Create_Value_Memtyp + (Hook_Bit_Rising_Edge.all (L, Res_Typ)); + end if; + raise Internal_Error; + when Iir_Predefined_Bit_Falling_Edge => + if Hook_Bit_Falling_Edge /= null then + return Create_Value_Memtyp + (Hook_Bit_Falling_Edge.all (L, Res_Typ)); + end if; + raise Internal_Error; when Iir_Predefined_Ieee_1164_Rising_Edge => if Hook_Std_Rising_Edge /= null then return Create_Value_Memtyp diff --git a/src/synth/synth-vhdl_oper.ads b/src/synth/synth-vhdl_oper.ads index 30d32820f..f02d4d55c 100644 --- a/src/synth/synth-vhdl_oper.ads +++ b/src/synth/synth-vhdl_oper.ads @@ -47,6 +47,9 @@ package Synth.Vhdl_Oper is type Eval_Predefined_Acc is access function (Param : Valtyp; Res_Typ : Type_Acc) return Memtyp; + Hook_Bit_Rising_Edge : Eval_Predefined_Acc; + Hook_Bit_Falling_Edge : Eval_Predefined_Acc; + Hook_Std_Rising_Edge : Eval_Predefined_Acc; Hook_Std_Falling_Edge : Eval_Predefined_Acc; end Synth.Vhdl_Oper; |