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author | Tristan Gingold <tgingold@free.fr> | 2019-10-07 20:59:47 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-10-07 20:59:47 +0200 |
commit | 7b2ccbe3cb679eb16bc5149a4ff282c9bc76dc43 (patch) | |
tree | a60b098898b4e3738df10d417c321a41d8b66977 | |
parent | ddcfde04823b714ea972c61cd368ca513acc648e (diff) | |
download | ghdl-7b2ccbe3cb679eb16bc5149a4ff282c9bc76dc43.tar.gz ghdl-7b2ccbe3cb679eb16bc5149a4ff282c9bc76dc43.tar.bz2 ghdl-7b2ccbe3cb679eb16bc5149a4ff282c9bc76dc43.zip |
synth: handle case statement on bit vectors.
-rw-r--r-- | src/synth/synth-stmts.adb | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/src/synth/synth-stmts.adb b/src/synth/synth-stmts.adb index 325836f8b..a127a7914 100644 --- a/src/synth/synth-stmts.adb +++ b/src/synth/synth-stmts.adb @@ -599,6 +599,29 @@ package body Synth.Stmts is end case; end loop; end; + elsif El_Type = Vhdl.Std_Package.Bit_Type_Definition then + declare + use Vhdl.Evaluation.String_Utils; + + Info : constant Str_Info := Get_Str_Info (Expr); + begin + if Info.Len > 64 then + raise Internal_Error; + end if; + Val := 0; + Dc := 0; + for I in 0 .. Info.Len - 1 loop + Val := Shift_Left (Val, 1); + case Get_Pos (Info, I) is + when 0 => + Val := Val or 0; + when 1 => + Val := Val or 1; + when others => + raise Internal_Error; + end case; + end loop; + end; else raise Internal_Error; end if; |