Fix bug15702: require generic association in direct entity instantiation.

3 files changed, 64 insertions, 9 deletions

diff --git a/sem.adb b/sem.adb
index be97ac6c3..f90b29b95 100644
--- a/sem.adb
+++ b/sem.adb
@@ -358,19 +358,17 @@ package body Sem is
             --  ...
             --  Each local port (or subelement or slice therof) must be
             --  associated {VHDL87: exactly}{VHDL93: at most} once.
-            if Flags.Vhdl_Std = Vhdl_87 then
+
+            --  GHDL: for a direct instantiation, follow rules of
+            --  LRM 1.1.1.1 Generic and LRM 1.1.1.2 Ports.
+            if Flags.Vhdl_Std = Vhdl_87
+              or else Get_Kind (Inter_Parent) = Iir_Kind_Entity_Declaration
+            then
                Miss_Generic := Missing_Generic;
                Miss_Port := Missing_Port;
             else
                Miss_Generic := Missing_Allowed;
-               if Get_Kind (Inter_Parent) = Iir_Kind_Entity_Declaration then
-                  --  FIXME: to be checked.
-                  --  Ghdl: for a direct instantiation, follow rules of
-                  --  LRM 1.1.1.2 Ports.
-                  Miss_Port := Missing_Port;
-               else
-                  Miss_Port := Missing_Allowed;
-               end if;
+               Miss_Port := Missing_Allowed;
             end if;
          when Iir_Kind_Binding_Indication =>
             --  LRM 5.2.1.2  Generic map and port map aspects
diff --git a/testsuite/gna/bug15702/example.vhd b/testsuite/gna/bug15702/example.vhd
new file mode 100644
index 000000000..3f0c8e7ab
--- /dev/null
+++ b/testsuite/gna/bug15702/example.vhd
@@ -0,0 +1,48 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+-- COMPONENT
+entity a is
+   -- N_BITS_DATA is nowhere initialized. This problem should be catched during
+   -- elaboration but it isn't !
+   -- During simulation I found that the value of N_BITS_DATA is -2147483648 and
+   -- that the value of N_BITS_DATA-1 is 2147483647 !!!!
+   generic (N_BITS_DATA : integer);
+end entity;
+
+architecture arch_a of a is
+   --~ -- Here data_s will have 4_194_305 elements and this will make ghdl
+   --~ -- take about 650 MB of memory. According to that, each element take about 150 B
+   --~ signal data_s : std_logic_vector((N_BITS_DATA-1)/512 downto 0);
+
+   -- This line make ghdl eat all the free memory because it is trying to make a
+   -- vector of 2**31 elements !!!! And there isn't enough memory because we need
+   -- about 2**31 * 150 B = ~ 300 GB !!!!
+   signal data_s : std_logic_vector(N_BITS_DATA-1 downto 0);
+
+   --~ -- Strangely this line doesn't make the simulation failed because N_BITS_DATA
+   --~ -- is negativ, but it doesn't increase the use of memory either.
+   --~ signal data_s : std_logic_vector(N_BITS_DATA downto 0);
+begin
+   process begin
+      -- N_BITS_DATA = -2147483648 = -2**31
+      report integer'image(N_BITS_DATA);
+      --
+      -- N_BITS_DATA-1 = 2147483647 = 2**31 - 1
+      report integer'image(N_BITS_DATA-1);
+      --
+      -- (N_BITS_DATA-1)/512 = 4_194_304 = 2**22
+      report integer'image((N_BITS_DATA-1)/512);
+      --
+   end process;
+end;
+--
+
+-- TESTBENCH
+entity tb is end entity;
+
+architecture arch_tb of tb is
+begin
+   X1: entity work.a;
+end;
+--
diff --git a/testsuite/gna/bug15702/testsuite.sh b/testsuite/gna/bug15702/testsuite.sh
new file mode 100755
index 000000000..e224bdbba
--- /dev/null
+++ b/testsuite/gna/bug15702/testsuite.sh
@@ -0,0 +1,9 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+analyze_failure example.vhd
+
+clean
+
+echo "Test successful"