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| author | Tristan Gingold <tgingold@free.fr> | 2022-10-19 05:24:42 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-10-19 05:24:42 +0200 |
| commit | 693466dceafbbca9cf060e4ee8e43b8abf1173cd (patch) | |
| tree | 193b657a417e899f049c1c904c5d95f571cac489 | |
| parent | fa0f97b6416f1015823f574f52c1343eb9058e16 (diff) | |
| download | ghdl-693466dceafbbca9cf060e4ee8e43b8abf1173cd.tar.gz ghdl-693466dceafbbca9cf060e4ee8e43b8abf1173cd.tar.bz2 ghdl-693466dceafbbca9cf060e4ee8e43b8abf1173cd.zip | |
synth-vhdl_oper: handle and_reduce. Fix #2224
| -rw-r--r-- | src/synth/synth-vhdl_oper.adb | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/src/synth/synth-vhdl_oper.adb b/src/synth/synth-vhdl_oper.adb index 1bbfbb133..960747266 100644 --- a/src/synth/synth-vhdl_oper.adb +++ b/src/synth/synth-vhdl_oper.adb @@ -2129,7 +2129,7 @@ package body Synth.Vhdl_Oper is return Synth_Dyadic_Int_Sgn (Ctxt, Id_Smax, L, R, Expr); when Iir_Predefined_Ieee_Std_Logic_Misc_Or_Reduce_Slv - | Iir_Predefined_Ieee_Std_Logic_Misc_Or_Reduce_Suv => + | Iir_Predefined_Ieee_Std_Logic_Misc_Or_Reduce_Suv => declare N : Net; begin @@ -2137,6 +2137,15 @@ package body Synth.Vhdl_Oper is Set_Location (N, Expr); return Create_Value_Net (N, Res_Typ); end; + when Iir_Predefined_Ieee_Std_Logic_Misc_And_Reduce_Slv + | Iir_Predefined_Ieee_Std_Logic_Misc_And_Reduce_Suv => + declare + N : Net; + begin + N := Build_Reduce (Ctxt, Id_Red_And, Get_Net (Ctxt, L)); + Set_Location (N, Expr); + return Create_Value_Net (N, Res_Typ); + end; when Iir_Predefined_Ieee_Numeric_Std_Match_Suv | Iir_Predefined_Ieee_Numeric_Std_Match_Slv => |