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| author | Tristan Gingold <tgingold@free.fr> | 2020-03-09 18:30:36 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-03-09 18:30:36 +0100 |
| commit | 664e84418a992b1a9d3977937ef1065970ed65ef (patch) | |
| tree | 5c94b193700b68469ec907abe9e8da156a93e4e0 | |
| parent | d39b3167068585948b8aab12a1cc02023b1eaf6b (diff) | |
| download | ghdl-664e84418a992b1a9d3977937ef1065970ed65ef.tar.gz ghdl-664e84418a992b1a9d3977937ef1065970ed65ef.tar.bz2 ghdl-664e84418a992b1a9d3977937ef1065970ed65ef.zip | |
synth: avoid crash on bad elaboration order.
| -rw-r--r-- | src/vhdl/vhdl-annotations.adb | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/vhdl/vhdl-annotations.adb b/src/vhdl/vhdl-annotations.adb index cf7659a22..aef7cafc0 100644 --- a/src/vhdl/vhdl-annotations.adb +++ b/src/vhdl/vhdl-annotations.adb @@ -741,7 +741,9 @@ package body Vhdl.Annotations is Annotate_Declaration_Type (Block_Info, Decl); Create_Signal_Info (Block_Info, Decl); when Iir_Kind_Anonymous_Signal_Declaration => - Create_Signal_Info (Block_Info, Decl); + if not Flag_Synthesis then + Create_Signal_Info (Block_Info, Decl); + end if; when Iir_Kind_Variable_Declaration | Iir_Kind_Iterator_Declaration => |