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author | Tristan Gingold <tgingold@free.fr> | 2020-02-01 11:21:30 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2020-02-01 11:21:30 +0100 |
commit | 579d59ed60396da77f015da6e86fce80c53dbeda (patch) | |
tree | 9426ed7f8b8a07208213be3a676b57f0006ec8e4 | |
parent | e6da991eca223785461e9c11501b391fb2c4e3ba (diff) | |
download | ghdl-579d59ed60396da77f015da6e86fce80c53dbeda.tar.gz ghdl-579d59ed60396da77f015da6e86fce80c53dbeda.tar.bz2 ghdl-579d59ed60396da77f015da6e86fce80c53dbeda.zip |
synth-inference: use the mux output to detect end of walk. Fix #1122
-rw-r--r-- | src/synth/synth-inference.adb | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/src/synth/synth-inference.adb b/src/synth/synth-inference.adb index 000b34045..728837f17 100644 --- a/src/synth/synth-inference.adb +++ b/src/synth/synth-inference.adb @@ -393,6 +393,7 @@ package body Synth.Inference is Rst_Val := No_Net; Rst := No_Net; declare + Done : Boolean; Mux : Instance; Sel : Net; Last_Out : Net; @@ -402,7 +403,11 @@ package body Synth.Inference is begin Last_Out := O; - while Is_Connected (Last_Out) loop + -- Initially, the final output is not connected. So walk from the + -- clocked mux until reaching the final output. + Done := not Is_Connected (Last_Out); + + while not Done loop if not Has_One_Connection (Last_Out) and then not Is_Const_Net (Last_Out) then @@ -428,6 +433,7 @@ package body Synth.Inference is end if; Last_Out := Get_Output (Mux, 0); + Done := not Is_Connected (Last_Out); if Is_Prev_FF_Value (Mux_Rst_Val, Prev_Val, Off) then -- The mux is like an enable. Like in this example, q2 is not @@ -466,6 +472,7 @@ package body Synth.Inference is Disconnect (Get_Mux2_I1 (Mux)); Disconnect (Get_Mux2_Sel (Mux)); + -- The output of the mux is now the reset value. Redirect_Inputs (Last_Out, Mux_Rst_Val); Free_Instance (Mux); |