simul: create initial driver value.

5 files changed, 67 insertions, 38 deletions

diff --git a/src/vhdl/simulate/simul-annotations.adb b/src/vhdl/simulate/simul-annotations.adb
index 21ab0a034..9db4aad02 100644
--- a/src/vhdl/simulate/simul-annotations.adb
+++ b/src/vhdl/simulate/simul-annotations.adb
@@ -66,8 +66,8 @@ package body Simul.Annotations is
             Info := new Sim_Info_Type'(Kind => Kind_Signal,
                                        Obj_Scope => Block_Info,
                                        Slot => Block_Info.Nbr_Objects);
-            --  Reserve one more slot for value.
-            Block_Info.Nbr_Objects := Block_Info.Nbr_Objects + 1;
+            --  Reserve one more slot for value, and initial driver value.
+            Block_Info.Nbr_Objects := Block_Info.Nbr_Objects + 2;
          when Kind_Terminal =>
             Info := new Sim_Info_Type'(Kind => Kind_Terminal,
                                        Obj_Scope => Block_Info,
diff --git a/src/vhdl/simulate/simul-elaboration.adb b/src/vhdl/simulate/simul-elaboration.adb
index 4396bb9cd..f2746b69c 100644
--- a/src/vhdl/simulate/simul-elaboration.adb
+++ b/src/vhdl/simulate/simul-elaboration.adb
@@ -108,7 +108,7 @@ package body Simul.Elaboration is
    is
       Slot : constant Object_Slot_Type := Get_Info (Decl).Slot;
    begin
-      Create_Object (Instance, Slot, 2);
+      Create_Object (Instance, Slot, 3);
    end Create_Signal;
 
    -- Create a new signal, using DEFAULT as initial value.
@@ -155,17 +155,19 @@ package body Simul.Elaboration is
          return Res;
       end Create_Signal;
 
+      Slot : constant Object_Slot_Type := Get_Info (Signal).Slot;
       Sig : Iir_Value_Literal_Acc;
       Def : Iir_Value_Literal_Acc;
-      Slot : constant Object_Slot_Type := Get_Info (Signal).Slot;
    begin
       Sig := Create_Signal (Default);
       Def := Unshare (Default, Global_Pool'Access);
       Block.Objects (Slot) := Sig;
       Block.Objects (Slot + 1) := Def;
+      Block.Objects (Slot + 2) := Unshare (Default, Global_Pool'Access);
 
       case Get_Kind (Signal) is
          when Iir_Kind_Interface_Signal_Declaration =>
+            --  Driver.
             case Get_Mode (Signal) is
                when Iir_Unknown_Mode =>
                   raise Internal_Error;
@@ -311,7 +313,7 @@ package body Simul.Elaboration is
       Create_Signal (Instance, Signal);
       Instance.Objects (Info.Slot) := Sig;
 
-      Init := Execute_Signal_Init_Value (Instance, Get_Prefix (Signal));
+      Init := Execute_Signal_Name (Instance, Get_Prefix (Signal), Signal_Val);
       Init := Unshare (Init, Global_Pool'Access); --  Create a full copy.
       Instance.Objects (Info.Slot + 1) := Init;
 
@@ -1322,8 +1324,8 @@ package body Simul.Elaboration is
                   Formal := Get_Association_Formal (Assoc, Inter);
                   if Is_Signal_Name (Actual) then
                      --  Association with a signal
-                     Init_Expr := Execute_Signal_Init_Value
-                       (Actual_Instance, Actual);
+                     Init_Expr := Execute_Signal_Name
+                       (Actual_Instance, Actual, Signal_Val);
                      Implicit_Array_Conversion
                        (Formal_Instance, Init_Expr, Get_Type (Formal), Actual);
                      Init_Expr := Unshare_Bounds
@@ -1374,12 +1376,17 @@ package body Simul.Elaboration is
                            Val := Execute_Expression_With_Type
                              (Formal_Instance, Default_Value,
                               Get_Type (Inter));
-                           Store (Formal_Instance.Objects (Slot + 1), Val);
+                           Val := Unshare (Val, Global_Pool'Access);
                         else
+                           Val := Unshare (Init_Expr, Global_Pool'Access);
                            Init_To_Default
-                             (Formal_Instance.Objects (Slot + 1),
-                              Formal_Instance, Get_Type (Inter));
+                             (Val, Formal_Instance, Get_Type (Inter));
                         end if;
+                        Formal_Instance.Objects (Slot + 2) := Val;
+                        Store (Formal_Instance.Objects (Slot + 1), Val);
+                     else
+                        -- Always set a value to the driver.
+                        Formal_Instance.Objects (Slot + 2) := Init_Expr;
                      end if;
                   end;
                else
diff --git a/src/vhdl/simulate/simul-execution.adb b/src/vhdl/simulate/simul-execution.adb
index 48c5470b1..990ff8e2e 100644
--- a/src/vhdl/simulate/simul-execution.adb
+++ b/src/vhdl/simulate/simul-execution.adb
@@ -2524,27 +2524,37 @@ package body Simul.Execution is
       end if;
    end Execute_Expression_With_Type;
 
-   function Execute_Signal_Init_Value (Block : Block_Instance_Acc; Expr : Iir)
-                                      return Iir_Value_Literal_Acc
+   function Execute_Signal_Name
+     (Block : Block_Instance_Acc; Expr : Iir; Kind : Signal_Slot)
+     return Iir_Value_Literal_Acc
    is
       Base : constant Iir := Get_Object_Prefix (Expr, False);
       Info : constant Sim_Info_Acc := Get_Info (Base);
       Bblk : Block_Instance_Acc;
+      Slot : Object_Slot_Type;
       Base_Val : Iir_Value_Literal_Acc;
       Res : Iir_Value_Literal_Acc;
       Is_Sig : Boolean;
    begin
       if Get_Kind (Base) = Iir_Kind_Object_Alias_Declaration then
          Bblk := Get_Instance_By_Scope (Block, Info.Obj_Scope);
-         Base_Val := Execute_Signal_Init_Value (Bblk, Get_Name (Base));
+         Base_Val := Execute_Signal_Name (Bblk, Get_Name (Base), Kind);
       else
          Bblk := Get_Instance_By_Scope (Block, Info.Obj_Scope);
-         Base_Val := Bblk.Objects (Info.Slot + 1);
+         case Kind is
+            when Signal_Sig =>
+               Slot := Info.Slot;
+            when Signal_Val =>
+               Slot := Info.Slot + 1;
+            when Signal_Init =>
+               Slot := Info.Slot + 2;
+         end case;
+         Base_Val := Bblk.Objects (Slot);
       end if;
       Execute_Name_With_Base (Block, Expr, Base_Val, Res, Is_Sig);
       pragma Assert (Is_Sig);
       return Res;
-   end Execute_Signal_Init_Value;
+   end Execute_Signal_Name;
 
    --  Indexed element will be at Pfx.Val_Array.V (Pos + 1)
    procedure Execute_Indexed_Name (Block: Block_Instance_Acc;
@@ -2728,7 +2738,6 @@ package body Simul.Execution is
 
          when Iir_Kind_Aggregate =>
             Res := Execute_Name_Aggregate (Block, Expr, Get_Type (Expr));
-            --  FIXME: is_sig ?
 
          when Iir_Kind_Image_Attribute =>
             Res := Execute_Image_Attribute (Block, Expr);
diff --git a/src/vhdl/simulate/simul-execution.ads b/src/vhdl/simulate/simul-execution.ads
index 566fa26db..276f283e3 100644
--- a/src/vhdl/simulate/simul-execution.ads
+++ b/src/vhdl/simulate/simul-execution.ads
@@ -87,10 +87,15 @@ package Simul.Execution is
       Formal_Instance : Block_Instance_Acc)
      return Iir_Value_Literal_Acc;
 
-   --  Return the initial value (default value) of signal name EXPR.  To be
-   --  used only during (non-dynamic) elaboration.
-   function Execute_Signal_Init_Value (Block : Block_Instance_Acc; Expr : Iir)
-                                      return Iir_Value_Literal_Acc;
+   --  There are up to three slots per instance for signals:
+   --  Signal_Sig: the signal (as handled by grt), with all its attribute
+   --  Signal_Val: the value of the signal (as assigned by grt).
+   --  Signal_Init: the initial value of drivers, only defined for ports.
+   type Signal_Slot is (Signal_Sig, Signal_Val, Signal_Init);
+
+   function Execute_Signal_Name
+     (Block : Block_Instance_Acc; Expr : Iir; Kind : Signal_Slot)
+     return Iir_Value_Literal_Acc;
 
    function Execute_Expression_With_Type
      (Block: Block_Instance_Acc;
diff --git a/src/vhdl/simulate/simul-simulation-main.adb b/src/vhdl/simulate/simul-simulation-main.adb
index 24f56f49b..47925c6e5 100644
--- a/src/vhdl/simulate/simul-simulation-main.adb
+++ b/src/vhdl/simulate/simul-simulation-main.adb
@@ -152,24 +152,29 @@ package body Simul.Simulation.Main is
    -- Add a driver for signal designed by VAL (via index field) for instance
    -- INSTANCE of process PROC.
    -- FIXME: default value.
-   procedure Add_Source
-     (Instance: Block_Instance_Acc; Val: Iir_Value_Literal_Acc; Proc: Iir)
-   is
+   procedure Add_Source (Instance : Block_Instance_Acc;
+                         Sig : Iir_Value_Literal_Acc;
+                         Val : Iir_Value_Literal_Acc) is
    begin
       case Val.Kind is
-         when Iir_Value_Signal =>
-            if Proc = Null_Iir then
-               -- Can this happen ?
-               raise Internal_Error;
-            end if;
-            Grt.Signals.Ghdl_Process_Add_Driver (Val.Sig);
+         when Iir_Value_B1 =>
+            Grt.Signals.Ghdl_Signal_Add_Port_Driver_B1 (Sig.Sig, Val.B1);
+         when Iir_Value_E8 =>
+            Grt.Signals.Ghdl_Signal_Add_Port_Driver_E8 (Sig.Sig, Val.E8);
+         when Iir_Value_E32 =>
+            Grt.Signals.Ghdl_Signal_Add_Port_Driver_E32 (Sig.Sig, Val.E32);
+         when Iir_Value_I64 =>
+            Grt.Signals.Ghdl_Signal_Add_Port_Driver_I64 (Sig.Sig, Val.I64);
+         when Iir_Value_F64 =>
+            Grt.Signals.Ghdl_Signal_Add_Port_Driver_F64 (Sig.Sig, Val.F64);
          when Iir_Value_Array =>
-            for I in Val.Val_Array.V'Range loop
-               Add_Source (Instance, Val.Val_Array.V (I), Proc);
+            for I in Sig.Val_Array.V'Range loop
+               Add_Source (Instance, Sig.Val_Array.V (I), Val.Val_Array.V (I));
             end loop;
          when Iir_Value_Record =>
-            for I in Val.Val_Record.V'Range loop
-               Add_Source (Instance, Val.Val_Record.V (I), Proc);
+            for I in Sig.Val_Record.V'Range loop
+               Add_Source
+                 (Instance, Sig.Val_Record.V (I), Val.Val_Record.V (I));
             end loop;
          when others =>
             raise Internal_Error;
@@ -183,7 +188,8 @@ package body Simul.Simulation.Main is
       Driver_List: Iir_List;
       It : List_Iterator;
       El: Iir;
-      Val: Iir_Value_Literal_Acc;
+      Val : Iir_Value_Literal_Acc;
+      Sig : Iir_Value_Literal_Acc;
       Marker : Mark_Type;
    begin
       if Trace_Drivers then
@@ -203,8 +209,11 @@ package body Simul.Simulation.Main is
          end if;
 
          Mark (Marker, Expr_Pool);
-         Val := Execute_Name (Instance, El, True);
-         Add_Source (Instance, Val, Proc);
+         --  The signal name is evaluated twice, but as it is globally static,
+         --  it shouldn't have any side-effect.  So not optimized but safe.
+         Sig := Execute_Signal_Name (Instance, El, Signal_Sig);
+         Val := Execute_Signal_Name (Instance, El, Signal_Init);
+         Add_Source (Instance, Sig, Val);
          Release (Marker, Expr_Pool);
 
          Next (It);
@@ -795,8 +804,7 @@ package body Simul.Simulation.Main is
    end Create_Connects;
 
    procedure Set_Disconnection (Val : Iir_Value_Literal_Acc;
-                                Time : Iir_Value_Time)
-   is
+                                Time : Iir_Value_Time) is
    begin
       case Val.Kind is
          when Iir_Value_Signal =>