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author | Tristan Gingold <tgingold@free.fr> | 2022-11-14 21:48:52 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2022-11-14 21:48:52 +0100 |
commit | 50fe9c3fbf77c02e2dd0ba4845671a7bccb3bf05 (patch) | |
tree | 92bb89642262d64564d691c519c7002583588331 | |
parent | 7fd8e9e2f8ea2e265bf0691fab8e8f35af0e8838 (diff) | |
download | ghdl-50fe9c3fbf77c02e2dd0ba4845671a7bccb3bf05.tar.gz ghdl-50fe9c3fbf77c02e2dd0ba4845671a7bccb3bf05.tar.bz2 ghdl-50fe9c3fbf77c02e2dd0ba4845671a7bccb3bf05.zip |
synth: avoid a crash on signal assignment in non-sensitized process.
Fix ghdl/ghdl-yosys-plugin#180
-rw-r--r-- | src/synth/synth-vhdl_stmts.adb | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/src/synth/synth-vhdl_stmts.adb b/src/synth/synth-vhdl_stmts.adb index 18525a4b6..8c521cc77 100644 --- a/src/synth/synth-vhdl_stmts.adb +++ b/src/synth/synth-vhdl_stmts.adb @@ -3723,7 +3723,12 @@ package body Synth.Vhdl_Stmts is when Iir_Kind_If_Statement => Synth_If_Statement (C, Stmt); when Iir_Kind_Simple_Signal_Assignment_Statement => - Synth_Simple_Signal_Assignment (C.Inst, Stmt); + if Is_Dyn then + Synth_Simple_Signal_Assignment (C.Inst, Stmt); + else + Error_Msg_Synth (C.Inst, Stmt, + "signal assignment not allowed here"); + end if; when Iir_Kind_Conditional_Signal_Assignment_Statement => Synth_Conditional_Signal_Assignment (C.Inst, Stmt); when Iir_Kind_Variable_Assignment_Statement => @@ -3896,7 +3901,9 @@ package body Synth.Vhdl_Stmts is Mark_Expr_Pool (Marker); - -- Handle the condition as an if. + -- The first statement is a wait statement, handle the condition + -- as an if. + pragma Assert (Get_Kind (Stmt) = Iir_Kind_Wait_Statement); Cond := Get_Condition_Clause (Stmt); if Cond = Null_Node then Error_Msg_Synth (C.Inst, Stmt, "expect wait condition"); |