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authorTristan Gingold <tgingold@free.fr>2020-04-14 08:20:29 +0200
committerTristan Gingold <tgingold@free.fr>2020-04-14 08:20:29 +0200
commit471f916e70306cf653f45bea40297ad8e7c84cc6 (patch)
tree7e9b10fbb155312b996dbf4d994a58653a820822
parent562a6eea44012b889dd7bfc97d7a4385d36b8157 (diff)
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synth-environment-debug: improve the debug code for wires.
-rw-r--r--src/synth/synth-environment-debug.adb21
-rw-r--r--src/synth/synth-environment-debug.ads2
2 files changed, 15 insertions, 8 deletions
diff --git a/src/synth/synth-environment-debug.adb b/src/synth/synth-environment-debug.adb
index 09eb9024f..81e8b17af 100644
--- a/src/synth/synth-environment-debug.adb
+++ b/src/synth/synth-environment-debug.adb
@@ -22,27 +22,26 @@ with Ada.Text_IO; use Ada.Text_IO;
with Netlists.Dump; use Netlists.Dump;
package body Synth.Environment.Debug is
- procedure Dump_Wire_Id (Id : Wire_Id)
+ procedure Dump_Wire (Wid : Wire_Id)
is
- W_Rec : Wire_Id_Record renames Wire_Id_Table.Table (Id);
+ W_Rec : Wire_Id_Record renames Wire_Id_Table.Table (Wid);
begin
- Put ("Wire:" & Wire_Id'Image (Id));
+ Put ("Wire:" & Wire_Id'Image (Wid));
Put_Line (" kind: " & Wire_Kind'Image (W_Rec.Kind));
Put_Line (" decl:" & Source.Syn_Src'Image (W_Rec.Decl));
Put (" gate: ");
- Dump_Net_Name (W_Rec.Gate);
+ Dump_Net_Name (W_Rec.Gate, True);
New_Line;
Put_Line (" cur_assign:" & Seq_Assign'Image (W_Rec.Cur_Assign));
Put_Line (" conc_assign:" & Conc_Assign'Image(W_Rec.Final_Assign));
- end Dump_Wire_Id;
+ end Dump_Wire;
procedure Dump_Partial_Assign (Pasgn : Partial_Assign)
is
procedure Dump_Value (N : Net) is
begin
if N /= No_Net then
- Dump_Net_Name (N);
- Put ("{w=" & Uns32'Image (Get_Width (N)) & '}');
+ Dump_Net_Name (N, True);
Put (" := ");
Disp_Instance (Get_Net_Parent (N), False, 0);
else
@@ -76,6 +75,14 @@ package body Synth.Environment.Debug is
Put (", phi:" & Phi_Id'Image (Rec.Phi));
Put (", chain:" & Seq_Assign'Image (Rec.Chain));
New_Line;
+ declare
+ W_Rec : Wire_Id_Record renames Wire_Id_Table.Table (Rec.Id);
+ begin
+ Put_Line (" wire decl:" & Source.Syn_Src'Image (W_Rec.Decl));
+ Put (" wire gate: ");
+ Dump_Net_Name (W_Rec.Gate, True);
+ New_Line;
+ end;
Put_Line (" value:");
if Rec.Val.Is_Static then
Put_Line (" static");
diff --git a/src/synth/synth-environment-debug.ads b/src/synth/synth-environment-debug.ads
index b45eb80ae..074608e2a 100644
--- a/src/synth/synth-environment-debug.ads
+++ b/src/synth/synth-environment-debug.ads
@@ -19,7 +19,7 @@
-- MA 02110-1301, USA.
package Synth.Environment.Debug is
- procedure Dump_Wire_Id (Id : Wire_Id);
+ procedure Dump_Wire (Wid : Wire_Id);
procedure Dump_Assign (Asgn : Seq_Assign);
procedure Dump_Conc_Assigns (First : Conc_Assign);
private