testsuite/synth: add testcase for previous commit.

3 files changed, 77 insertions, 0 deletions

diff --git a/testsuite/synth/case02/case01.vhdl b/testsuite/synth/case02/case01.vhdl
new file mode 100644
index 000000000..702d7244c
--- /dev/null
+++ b/testsuite/synth/case02/case01.vhdl
@@ -0,0 +1,29 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity case01 is
+  port (a : std_logic_vector (1 downto 0);
+        clk : std_logic;
+        o : out std_logic_vector(1 downto 0));
+end case01;
+
+architecture behav of case01 is
+begin
+  process (clk)
+  begin
+    if rising_edge (clk) then
+      case a is
+        when "01" =>
+          o (0) <= '1';
+        when "11" =>
+          o (1) <= '1';
+        when "00" =>
+          o (0) <= '0';
+        when "10" =>
+          o (1) <= '0';
+        when others =>
+          o <= "00";
+      end case;
+    end if;
+  end process;
+end behav;
diff --git a/testsuite/synth/case02/tb_case01.vhdl b/testsuite/synth/case02/tb_case01.vhdl
new file mode 100644
index 000000000..95b8561d8
--- /dev/null
+++ b/testsuite/synth/case02/tb_case01.vhdl
@@ -0,0 +1,32 @@
+entity tb_case01 is
+end tb_case01;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_case01 is
+  signal a : std_logic_vector (1 downto 0);
+  signal o : std_logic_vector (1 downto 0);
+  signal clk : std_logic;
+begin
+  dut: entity work.case01
+    port map (a, clk, o);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    a <= "00";
+    pulse;
+    a <= "10";
+    pulse;
+    assert o = "00" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/case02/testsuite.sh b/testsuite/synth/case02/testsuite.sh
new file mode 100755
index 000000000..fe81cddf9
--- /dev/null
+++ b/testsuite/synth/case02/testsuite.sh
@@ -0,0 +1,16 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+for t in case01; do
+    analyze $t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t
+    clean
+
+    synth $t.vhdl -e $t > syn_$t.vhdl
+    analyze syn_$t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t
+    clean
+done
+
+echo "Test successful"