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authorTristan Gingold <tgingold@free.fr>2019-10-26 08:28:27 +0200
committerTristan Gingold <tgingold@free.fr>2019-10-26 08:28:27 +0200
commit334e6277a5ac7a0f04c26a3b274ab8db7b7020a7 (patch)
treee76f090b57ed839b89d142bed27b68effd344581
parent7004234586989df260a587f284f9a345142f0a01 (diff)
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testsuite/synth/psl02: renaming.
-rw-r--r--testsuite/synth/psl02/verif3.vhdl2
1 files changed, 1 insertions, 1 deletions
diff --git a/testsuite/synth/psl02/verif3.vhdl b/testsuite/synth/psl02/verif3.vhdl
index c1b262177..abc5ad220 100644
--- a/testsuite/synth/psl02/verif3.vhdl
+++ b/testsuite/synth/psl02/verif3.vhdl
@@ -1,4 +1,4 @@
-vunit verif2 (assert2(behav))
+vunit verif3 (assert2(behav))
{
default clock is rising_edge(clk);
assume always val < 10;