vhdl: recognize numeric_std shift_left.

6 files changed, 254 insertions, 220 deletions

diff --git a/python/libghdl/thin/std_names.py b/python/libghdl/thin/std_names.py
index e84884895..9b3fa32be 100644
--- a/python/libghdl/thin/std_names.py
+++ b/python/libghdl/thin/std_names.py
@@ -590,174 +590,176 @@ class Name:
     To_Signed = 804
     Resize = 805
     Std_Match = 806
-    Math_Real = 807
-    Ceil = 808
-    Log2 = 809
-    Last_Ieee = 809
-    First_Directive = 810
-    Define = 810
-    Endif = 811
-    Ifdef = 812
-    Ifndef = 813
-    Include = 814
-    Timescale = 815
-    Undef = 816
-    Protect = 817
-    Begin_Protected = 818
-    End_Protected = 819
-    Key_Block = 820
-    Data_Block = 821
-    Line = 822
-    Celldefine = 823
-    Endcelldefine = 824
-    Default_Nettype = 825
-    Resetall = 826
-    Last_Directive = 826
-    First_Systask = 827
-    Bits = 827
-    D_Root = 828
-    D_Unit = 829
-    Last_Systask = 829
-    First_SV_Method = 830
-    Size = 830
-    Insert = 831
-    Delete = 832
-    Pop_Front = 833
-    Pop_Back = 834
-    Push_Front = 835
-    Push_Back = 836
-    Name = 837
-    Len = 838
-    Substr = 839
-    Exists = 840
-    Atoi = 841
-    Itoa = 842
-    Find = 843
-    Find_Index = 844
-    Find_First = 845
-    Find_First_Index = 846
-    Find_Last = 847
-    Find_Last_Index = 848
-    Num = 849
-    Randomize = 850
-    Pre_Randomize = 851
-    Post_Randomize = 852
-    Srandom = 853
-    Get_Randstate = 854
-    Set_Randstate = 855
-    Seed = 856
-    State = 857
-    Last_SV_Method = 857
-    First_BSV = 858
-    uAction = 858
-    uActionValue = 859
-    BVI = 860
-    uC = 861
-    uCF = 862
-    uE = 863
-    uSB = 864
-    uSBR = 865
-    Action = 866
-    Endaction = 867
-    Actionvalue = 868
-    Endactionvalue = 869
-    Ancestor = 870
-    Clocked_By = 871
-    Default_Clock = 872
-    Default_Reset = 873
-    Dependencies = 874
-    Deriving = 875
-    Determines = 876
-    Enable = 877
-    Ifc_Inout = 878
-    Input_Clock = 879
-    Input_Reset = 880
-    Instance = 881
-    Endinstance = 882
-    Let = 883
-    Match = 884
-    Method = 885
-    Endmethod = 886
-    Numeric = 887
-    Output_Clock = 888
-    Output_Reset = 889
-    Par = 890
-    Endpar = 891
-    Path = 892
-    Provisos = 893
-    Ready = 894
-    Reset_By = 895
-    Rule = 896
-    Endrule = 897
-    Rules = 898
-    Endrules = 899
-    Same_Family = 900
-    Schedule = 901
-    Seq = 902
-    Endseq = 903
-    Typeclass = 904
-    Endtypeclass = 905
-    Valueof = 906
-    uValueof = 907
-    Last_BSV = 907
-    First_Comment = 908
-    Psl = 908
-    Pragma = 909
-    Last_Comment = 909
-    First_PSL = 910
-    A = 910
-    Af = 911
-    Ag = 912
-    Ax = 913
-    Abort = 914
-    Assume_Guarantee = 915
-    Before = 916
-    Clock = 917
-    E = 918
-    Ef = 919
-    Eg = 920
-    Ex = 921
-    Endpoint = 922
-    Eventually = 923
-    Fairness = 924
-    Fell = 925
-    Forall = 926
-    G = 927
-    Inf = 928
-    Inherit = 929
-    Never = 930
-    Next_A = 931
-    Next_E = 932
-    Next_Event = 933
-    Next_Event_A = 934
-    Next_Event_E = 935
-    Prev = 936
-    Rose = 937
-    Strong = 938
-    W = 939
-    Whilenot = 940
-    Within = 941
-    X = 942
-    Last_PSL = 942
-    First_Edif = 943
-    Celltype = 953
-    View = 954
-    Viewtype = 955
-    Direction = 956
-    Contents = 957
-    Net = 958
-    Viewref = 959
-    Cellref = 960
-    Libraryref = 961
-    Portinstance = 962
-    Joined = 963
-    Portref = 964
-    Instanceref = 965
-    Design = 966
-    Designator = 967
-    Owner = 968
-    Member = 969
-    Number = 970
-    Rename = 971
-    Userdata = 972
-    Last_Edif = 972
+    Shift_Left = 807
+    Shift_Right = 808
+    Math_Real = 809
+    Ceil = 810
+    Log2 = 811
+    Last_Ieee = 811
+    First_Directive = 812
+    Define = 812
+    Endif = 813
+    Ifdef = 814
+    Ifndef = 815
+    Include = 816
+    Timescale = 817
+    Undef = 818
+    Protect = 819
+    Begin_Protected = 820
+    End_Protected = 821
+    Key_Block = 822
+    Data_Block = 823
+    Line = 824
+    Celldefine = 825
+    Endcelldefine = 826
+    Default_Nettype = 827
+    Resetall = 828
+    Last_Directive = 828
+    First_Systask = 829
+    Bits = 829
+    D_Root = 830
+    D_Unit = 831
+    Last_Systask = 831
+    First_SV_Method = 832
+    Size = 832
+    Insert = 833
+    Delete = 834
+    Pop_Front = 835
+    Pop_Back = 836
+    Push_Front = 837
+    Push_Back = 838
+    Name = 839
+    Len = 840
+    Substr = 841
+    Exists = 842
+    Atoi = 843
+    Itoa = 844
+    Find = 845
+    Find_Index = 846
+    Find_First = 847
+    Find_First_Index = 848
+    Find_Last = 849
+    Find_Last_Index = 850
+    Num = 851
+    Randomize = 852
+    Pre_Randomize = 853
+    Post_Randomize = 854
+    Srandom = 855
+    Get_Randstate = 856
+    Set_Randstate = 857
+    Seed = 858
+    State = 859
+    Last_SV_Method = 859
+    First_BSV = 860
+    uAction = 860
+    uActionValue = 861
+    BVI = 862
+    uC = 863
+    uCF = 864
+    uE = 865
+    uSB = 866
+    uSBR = 867
+    Action = 868
+    Endaction = 869
+    Actionvalue = 870
+    Endactionvalue = 871
+    Ancestor = 872
+    Clocked_By = 873
+    Default_Clock = 874
+    Default_Reset = 875
+    Dependencies = 876
+    Deriving = 877
+    Determines = 878
+    Enable = 879
+    Ifc_Inout = 880
+    Input_Clock = 881
+    Input_Reset = 882
+    Instance = 883
+    Endinstance = 884
+    Let = 885
+    Match = 886
+    Method = 887
+    Endmethod = 888
+    Numeric = 889
+    Output_Clock = 890
+    Output_Reset = 891
+    Par = 892
+    Endpar = 893
+    Path = 894
+    Provisos = 895
+    Ready = 896
+    Reset_By = 897
+    Rule = 898
+    Endrule = 899
+    Rules = 900
+    Endrules = 901
+    Same_Family = 902
+    Schedule = 903
+    Seq = 904
+    Endseq = 905
+    Typeclass = 906
+    Endtypeclass = 907
+    Valueof = 908
+    uValueof = 909
+    Last_BSV = 909
+    First_Comment = 910
+    Psl = 910
+    Pragma = 911
+    Last_Comment = 911
+    First_PSL = 912
+    A = 912
+    Af = 913
+    Ag = 914
+    Ax = 915
+    Abort = 916
+    Assume_Guarantee = 917
+    Before = 918
+    Clock = 919
+    E = 920
+    Ef = 921
+    Eg = 922
+    Ex = 923
+    Endpoint = 924
+    Eventually = 925
+    Fairness = 926
+    Fell = 927
+    Forall = 928
+    G = 929
+    Inf = 930
+    Inherit = 931
+    Never = 932
+    Next_A = 933
+    Next_E = 934
+    Next_Event = 935
+    Next_Event_A = 936
+    Next_Event_E = 937
+    Prev = 938
+    Rose = 939
+    Strong = 940
+    W = 941
+    Whilenot = 942
+    Within = 943
+    X = 944
+    Last_PSL = 944
+    First_Edif = 945
+    Celltype = 955
+    View = 956
+    Viewtype = 957
+    Direction = 958
+    Contents = 959
+    Net = 960
+    Viewref = 961
+    Cellref = 962
+    Libraryref = 963
+    Portinstance = 964
+    Joined = 965
+    Portref = 966
+    Instanceref = 967
+    Design = 968
+    Designator = 969
+    Owner = 970
+    Member = 971
+    Number = 972
+    Rename = 973
+    Userdata = 974
+    Last_Edif = 974
diff --git a/python/libghdl/thin/vhdl/nodes.py b/python/libghdl/thin/vhdl/nodes.py
index 8c3a40530..8dbc7a092 100644
--- a/python/libghdl/thin/vhdl/nodes.py
+++ b/python/libghdl/thin/vhdl/nodes.py
@@ -1129,52 +1129,56 @@ class Iir_Predefined:
     Ieee_Numeric_Std_Ne_Sgn_Sgn = 254
     Ieee_Numeric_Std_Ne_Sgn_Int = 255
     Ieee_Numeric_Std_Ne_Int_Sgn = 256
-    Ieee_Numeric_Std_Not_Uns = 257
-    Ieee_Numeric_Std_Not_Sgn = 258
-    Ieee_Numeric_Std_And_Uns_Uns = 259
-    Ieee_Numeric_Std_And_Sgn_Sgn = 260
-    Ieee_Numeric_Std_Or_Uns_Uns = 261
-    Ieee_Numeric_Std_Or_Sgn_Sgn = 262
-    Ieee_Numeric_Std_Nand_Uns_Uns = 263
-    Ieee_Numeric_Std_Nand_Sgn_Sgn = 264
-    Ieee_Numeric_Std_Nor_Uns_Uns = 265
-    Ieee_Numeric_Std_Nor_Sgn_Sgn = 266
-    Ieee_Numeric_Std_Xor_Uns_Uns = 267
-    Ieee_Numeric_Std_Xor_Sgn_Sgn = 268
-    Ieee_Numeric_Std_Xnor_Uns_Uns = 269
-    Ieee_Numeric_Std_Xnor_Sgn_Sgn = 270
-    Ieee_Numeric_Std_Neg_Uns = 271
-    Ieee_Numeric_Std_Neg_Sgn = 272
-    Ieee_Numeric_Std_Match_Log = 273
-    Ieee_Numeric_Std_Match_Uns = 274
-    Ieee_Numeric_Std_Match_Sgn = 275
-    Ieee_Numeric_Std_Match_Slv = 276
-    Ieee_Numeric_Std_Match_Suv = 277
-    Ieee_Math_Real_Ceil = 278
-    Ieee_Math_Real_Log2 = 279
-    Ieee_Std_Logic_Unsigned_Add_Slv_Slv = 280
-    Ieee_Std_Logic_Unsigned_Add_Slv_Int = 281
-    Ieee_Std_Logic_Unsigned_Add_Int_Slv = 282
-    Ieee_Std_Logic_Unsigned_Add_Slv_Sl = 283
-    Ieee_Std_Logic_Unsigned_Add_Sl_Slv = 284
-    Ieee_Std_Logic_Unsigned_Lt_Slv_Slv = 285
-    Ieee_Std_Logic_Unsigned_Lt_Slv_Int = 286
-    Ieee_Std_Logic_Unsigned_Lt_Int_Slv = 287
-    Ieee_Std_Logic_Unsigned_Le_Slv_Slv = 288
-    Ieee_Std_Logic_Unsigned_Le_Slv_Int = 289
-    Ieee_Std_Logic_Unsigned_Le_Int_Slv = 290
-    Ieee_Std_Logic_Unsigned_Gt_Slv_Slv = 291
-    Ieee_Std_Logic_Unsigned_Gt_Slv_Int = 292
-    Ieee_Std_Logic_Unsigned_Gt_Int_Slv = 293
-    Ieee_Std_Logic_Unsigned_Ge_Slv_Slv = 294
-    Ieee_Std_Logic_Unsigned_Ge_Slv_Int = 295
-    Ieee_Std_Logic_Unsigned_Ge_Int_Slv = 296
-    Ieee_Std_Logic_Unsigned_Eq_Slv_Slv = 297
-    Ieee_Std_Logic_Unsigned_Eq_Slv_Int = 298
-    Ieee_Std_Logic_Unsigned_Eq_Int_Slv = 299
-    Ieee_Std_Logic_Unsigned_Ne_Slv_Slv = 300
-    Ieee_Std_Logic_Unsigned_Ne_Slv_Int = 301
-    Ieee_Std_Logic_Unsigned_Ne_Int_Slv = 302
+    Ieee_Numeric_Std_Shl_Uns_Nat = 257
+    Ieee_Numeric_Std_Shr_Uns_Nat = 258
+    Ieee_Numeric_Std_Shl_Sgn_Nat = 259
+    Ieee_Numeric_Std_Shr_Sgn_Nat = 260
+    Ieee_Numeric_Std_Not_Uns = 261
+    Ieee_Numeric_Std_Not_Sgn = 262
+    Ieee_Numeric_Std_And_Uns_Uns = 263
+    Ieee_Numeric_Std_And_Sgn_Sgn = 264
+    Ieee_Numeric_Std_Or_Uns_Uns = 265
+    Ieee_Numeric_Std_Or_Sgn_Sgn = 266
+    Ieee_Numeric_Std_Nand_Uns_Uns = 267
+    Ieee_Numeric_Std_Nand_Sgn_Sgn = 268
+    Ieee_Numeric_Std_Nor_Uns_Uns = 269
+    Ieee_Numeric_Std_Nor_Sgn_Sgn = 270
+    Ieee_Numeric_Std_Xor_Uns_Uns = 271
+    Ieee_Numeric_Std_Xor_Sgn_Sgn = 272
+    Ieee_Numeric_Std_Xnor_Uns_Uns = 273
+    Ieee_Numeric_Std_Xnor_Sgn_Sgn = 274
+    Ieee_Numeric_Std_Neg_Uns = 275
+    Ieee_Numeric_Std_Neg_Sgn = 276
+    Ieee_Numeric_Std_Match_Log = 277
+    Ieee_Numeric_Std_Match_Uns = 278
+    Ieee_Numeric_Std_Match_Sgn = 279
+    Ieee_Numeric_Std_Match_Slv = 280
+    Ieee_Numeric_Std_Match_Suv = 281
+    Ieee_Math_Real_Ceil = 282
+    Ieee_Math_Real_Log2 = 283
+    Ieee_Std_Logic_Unsigned_Add_Slv_Slv = 284
+    Ieee_Std_Logic_Unsigned_Add_Slv_Int = 285
+    Ieee_Std_Logic_Unsigned_Add_Int_Slv = 286
+    Ieee_Std_Logic_Unsigned_Add_Slv_Sl = 287
+    Ieee_Std_Logic_Unsigned_Add_Sl_Slv = 288
+    Ieee_Std_Logic_Unsigned_Lt_Slv_Slv = 289
+    Ieee_Std_Logic_Unsigned_Lt_Slv_Int = 290
+    Ieee_Std_Logic_Unsigned_Lt_Int_Slv = 291
+    Ieee_Std_Logic_Unsigned_Le_Slv_Slv = 292
+    Ieee_Std_Logic_Unsigned_Le_Slv_Int = 293
+    Ieee_Std_Logic_Unsigned_Le_Int_Slv = 294
+    Ieee_Std_Logic_Unsigned_Gt_Slv_Slv = 295
+    Ieee_Std_Logic_Unsigned_Gt_Slv_Int = 296
+    Ieee_Std_Logic_Unsigned_Gt_Int_Slv = 297
+    Ieee_Std_Logic_Unsigned_Ge_Slv_Slv = 298
+    Ieee_Std_Logic_Unsigned_Ge_Slv_Int = 299
+    Ieee_Std_Logic_Unsigned_Ge_Int_Slv = 300
+    Ieee_Std_Logic_Unsigned_Eq_Slv_Slv = 301
+    Ieee_Std_Logic_Unsigned_Eq_Slv_Int = 302
+    Ieee_Std_Logic_Unsigned_Eq_Int_Slv = 303
+    Ieee_Std_Logic_Unsigned_Ne_Slv_Slv = 304
+    Ieee_Std_Logic_Unsigned_Ne_Slv_Int = 305
+    Ieee_Std_Logic_Unsigned_Ne_Int_Slv = 306
 
 Get_Kind = libghdl.vhdl__nodes__get_kind
 Get_Location = libghdl.vhdl__nodes__get_location
diff --git a/src/std_names.adb b/src/std_names.adb
index 34aae433c..7552a4097 100644
--- a/src/std_names.adb
+++ b/src/std_names.adb
@@ -642,6 +642,8 @@ package body Std_Names is
       Def ("to_signed",          Name_To_Signed);
       Def ("resize",             Name_Resize);
       Def ("std_match",          Name_Std_Match);
+      Def ("shift_left",         Name_Shift_Left);
+      Def ("shift_right",        Name_Shift_Right);
       Def ("math_real",          Name_Math_Real);
       Def ("ceil",               Name_Ceil);
       Def ("log2",               Name_Log2);
diff --git a/src/std_names.ads b/src/std_names.ads
index e20db31a9..3af9e6082 100644
--- a/src/std_names.ads
+++ b/src/std_names.ads
@@ -723,9 +723,11 @@ package Std_Names is
    Name_To_Signed          : constant Name_Id := Name_First_Ieee + 021;
    Name_Resize             : constant Name_Id := Name_First_Ieee + 022;
    Name_Std_Match          : constant Name_Id := Name_First_Ieee + 023;
-   Name_Math_Real          : constant Name_Id := Name_First_Ieee + 024;
-   Name_Ceil               : constant Name_Id := Name_First_Ieee + 025;
-   Name_Log2               : constant Name_Id := Name_First_Ieee + 026;
+   Name_Shift_Left         : constant Name_Id := Name_First_Ieee + 024;
+   Name_Shift_Right        : constant Name_Id := Name_First_Ieee + 025;
+   Name_Math_Real          : constant Name_Id := Name_First_Ieee + 026;
+   Name_Ceil               : constant Name_Id := Name_First_Ieee + 027;
+   Name_Log2               : constant Name_Id := Name_First_Ieee + 028;
    Name_Last_Ieee          : constant Name_Id := Name_Log2;
 
    --  Verilog Directives.
diff --git a/src/vhdl/vhdl-ieee-numeric.adb b/src/vhdl/vhdl-ieee-numeric.adb
index 4d5c0d5e3..500c0a260 100644
--- a/src/vhdl/vhdl-ieee-numeric.adb
+++ b/src/vhdl/vhdl-ieee-numeric.adb
@@ -477,6 +477,8 @@ package body Vhdl.Ieee.Numeric is
 
          Set_Implicit_Definition (Decl, Predefined);
       end Handle_Std_Match;
+
+      Res : Iir_Predefined_Functions;
    begin
       Decl := Get_Declaration_Chain (Pkg_Decl);
 
@@ -589,6 +591,23 @@ package body Vhdl.Ieee.Numeric is
                         Handle_Resize;
                      when Name_Std_Match =>
                         Handle_Std_Match;
+                     when Name_Shift_Left =>
+                        if Arg1_Kind = Arg_Vect
+                          and then Arg2_Kind = Arg_Scal
+                          and then Arg2_Sign = Type_Unsigned
+                        then
+                           case Arg1_Sign is
+                              when Type_Signed =>
+                                 Res :=
+                                   Iir_Predefined_Ieee_Numeric_Std_Shl_Sgn_Nat;
+                              when Type_Unsigned =>
+                                 Res :=
+                                   Iir_Predefined_Ieee_Numeric_Std_Shl_Uns_Nat;
+                              when others =>
+                                 Res := Iir_Predefined_None;
+                           end case;
+                           Set_Implicit_Definition (Decl, Res);
+                        end if;
                      when others =>
                         null;
                   end case;
diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads
index 93407a5df..de1df09e9 100644
--- a/src/vhdl/vhdl-nodes.ads
+++ b/src/vhdl/vhdl-nodes.ads
@@ -4992,6 +4992,11 @@ package Vhdl.Nodes is
       Iir_Predefined_Ieee_Numeric_Std_Ne_Sgn_Int,
       Iir_Predefined_Ieee_Numeric_Std_Ne_Int_Sgn,
 
+      Iir_Predefined_Ieee_Numeric_Std_Shl_Uns_Nat,
+      Iir_Predefined_Ieee_Numeric_Std_Shr_Uns_Nat,
+      Iir_Predefined_Ieee_Numeric_Std_Shl_Sgn_Nat,
+      Iir_Predefined_Ieee_Numeric_Std_Shr_Sgn_Nat,
+
       Iir_Predefined_Ieee_Numeric_Std_Not_Uns,
       Iir_Predefined_Ieee_Numeric_Std_Not_Sgn,